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PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use PM7329 s /uni - a pex-1k80 0 tm s/uni-apex-1k800 atm/packet traffic manager and switch datasheet issue 2: june, 2001
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use revision history issue no. issue date details of change issue 1 february, 2001 document created. issue 2 june, 2001 document revision
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use i contents 1 definitions .......................................................................................... 1 2 features .............................................................................................. 3 3 applications ....................................................................................... 7 4 references ......................................................................................... 8 5 application examples ..................................................................... 9 6 block diagram ................................................................................. 10 7 description ...................................................................................... 12 8 pin diagram ....................................................................................... 16 9 pin description ................................................................................ 17 9.1 loop any-phy receive master/transmit slave interface (28 signals) ........................................................ 17 9.2 loop any-phy transmit master/receive slave interface (34 signals) ........................................................ 22 9.3 wan any-phy receive master/transmit slave interface (25 signals) ........................................................ 26 9.4 wan any-phy transmit master/receive slave interface (25 signals) ........................................................ 31 9.5 context memory synchronous ssram interface (59 signals) .................................................................................... 36 9.6 cell buffer sdram interface (52 signals) ................. 38 9.7 microprocessor interface (44 signals) ..................... 40 9.8 general (10 signals) ........................................................... 44 9.9 jtag & scan interface (7 signals) .................................. 45 9.10 power ....................................................................................... 47 10 functional description ................................................................. 49
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use ii 10.1 any-phy interfaces ............................................................. 49 10.1.1 receive interface ..................................................... 49 10.1.2 transmit interface .................................................. 51 10.2 loop port scheduler ........................................................ 54 10.3 wan port scheduler .......................................................... 55 10.4 wan port aliasing ................................................................ 57 10.5 wan and loop ici selection .............................................. 58 10.6 microprocessor interface ............................................ 58 10.7 memory port ......................................................................... 62 10.8 sar assist ............................................................................... 63 10.8.1 transmit ....................................................................... 63 10.8.2 receive .......................................................................... 64 10.9 queue engine ......................................................................... 65 10.9.1 service arbitration ................................................. 66 10.9.2 cell queuing ............................................................... 67 10.9.3 class scheduling ..................................................... 74 10.9.4 congestion control ............................................... 76 10.9.5 statistics ..................................................................... 83 10.9.6 microprocessor queue buffer re- allocation/tear down ............................................ 85 10.10 context memory ssram interface ................................ 85 10.11 cell buffer sdram interface ......................................... 90 10.12 jtag test access port ....................................................... 93 11 performance ................................................................................... 94 11.1 throughput ........................................................................... 94
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use iii 11.2 latency .................................................................................... 96 11.3 cdv ............................................................................................. 96 12 register ............................................................................................. 97 12.1 general configuration and status .............................. 98 12.2 loop cell interface ......................................................... 107 12.3 wan cell interface ............................................................113 12.4 memory port ........................................................................119 12.5 sar ........................................................................................... 125 12.5.1 receive ........................................................................ 125 12.5.2 transmit ..................................................................... 127 12.5.3 cell buffer diagnostic access ......................... 128 12.6 queue engine ....................................................................... 129 12.7 memory interface ............................................................. 144 12.8 cbi interface ....................................................................... 145 13 cbi register port mapping ....................................................... 147 14 memory port mapping ................................................................. 153 14.1 context size and location ............................................. 153 14.2 queue context definition .............................................. 156 14.2.1 vc context records .............................................. 157 14.2.2 port context records ......................................... 165 14.2.3 class context records ....................................... 169 14.2.4 shaping context records ................................... 174 14.2.5 cell context record ............................................ 176 14.2.6 misc context ............................................................ 176
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use iv 14.3 wan port scheduler context ...................................... 180 14.3.1 wan transmit port polling weight record . 180 14.3.2 wan transmit class status record ................ 181 14.4 loop port scheduler context .................................... 182 14.4.1 loop transmit port polling sequence record 182 14.4.2 loop transmit port polling weight record 183 14.4.3 loop transmit class status record ............... 184 15 test features description ...................................................... 186 15.1 jtag test port .................................................................... 186 16 operation ......................................................................................... 190 17 functional timing ......................................................................... 191 17.1 microprocessor interface .......................................... 191 17.2 sdram interface ................................................................ 193 17.3 zbt ssram interface ......................................................... 195 17.4 late write ssram interface .......................................... 196 17.5 any-phy/utopia interfaces ............................................. 197 17.5.1 receive master/transmit slave interfaces . 197 17.5.2 transmit master/receive slave interfaces . 200 18 absolute maximum ratings ....................................................... 205 19 d.c. characteristics ................................................................... 206 20 a.c. timing characteristics ...................................................... 208 20.1 jtag interface .................................................................... 213 21 ordering and thermal information ...................................... 215 22 mechanical information ............................................................ 216
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use v list of registers register 0x00: reset and identity ...................................................... 98 register 0x10: hi priority interrupt status register ............... 99 register 0x14: high priority interrupt mask ............................... 101 register 0x18: low priority interrupt error register ......... 102 register 0x1c: low priority interrupt error mask ................. 104 register 0x20: low priority interrupt status register ........ 105 register 0x24: low priority interrupt status mask ................. 106 register 0x100: loop cell rx interface configuration ........... 107 register 0x104: loop cell tx interface configuration ............110 register 0x200: wan cell rx interface configuration .............113 register 0x204: wan cell tx interface configuration .............116 register 0x300: memory port control ............................................119 register 0x340-0x34c: memory write data (burstable) ............. 121 register 0x350: memory write data overflow (burstable) ... 122 register 0x380-0x38c: memory read data (burstable) ............... 123 register 0x390: memory read data overflow (burstable) ..... 124 register 0x400-0x43c: sar receive data (burstable) .................. 125 register 0x500-0x53c: sar transmit data, class 0 (burstable) 127 register 0x540-0x57c: sar transmit data, class 1 (burstable) 127 register 0x580-0x5bc: sar transmit data, class 2 (burstable) 127 register 0x5c0-0x5fc: sar transmit data, class 3 (burstable) 127 register 0x600: cell buffer diagnostic control ...................... 128
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use vi register 0x700: queue context configuration .......................... 129 register 0x704: receive and transmit control .......................... 132 register 0x710: max direction congestion thresholds ......... 134 register 0x714: clp0 direction congestion thresholds ........ 135 register 0x718: clp1 direction congestion thresholds ........ 136 register 0x71c: re-assembly maximum length ............................. 137 register 0x720: watch dog ici patrol range ................................ 138 register 0x724: tear down queue id ................................................ 139 register 0x728: watch dog / tear down status .......................... 140 register 0x730: shaper 0 configuration (n = 0) ............................ 141 register 0x734: shaper 1 configuration (n = 1) ............................ 141 register 0x738: shaper 2 configuration (n = 2) ............................ 141 register 0x73c: shaper 3 configuration (n = 3) ........................... 141 register 0x800: sdram/ssram configuration ............................... 144 register 0xa00: cbi register port ................................................... 145 cbi register 0x00: configuration ..................................................... 147 cbi register 0x01: vernier control ................................................. 149 cbi register 0x02: delay tap status ................................................. 150 cbi register 0x03: control status ................................................... 151
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use vii list of figures figure 1 - s/uni-apex-1k800 in oc3 mini-dslam application ............ 7 figure 2 - s/uni-apex-1k800 block diagram with datapath ..........11 figure 3 - s/uni-apex-1k800 bottom view pin out ........................... 16 figure 4 - 16bit receive cell transfer format ............................. 49 figure 5 - 8-bit receive cell transfer format ............................. 50 figure 6 - 16-bit transmit cell transfer format ......................... 52 figure 7 - 8-bit transmit cell transfer format ........................... 53 figure 8 - i960 (80960cf) interface ....................................................... 61 figure 9 - powerpc (mpc860) interface ............................................ 61 figure 10- sar assist transmit cell transfer format ............... 64 figure 11 - sar assist receive cell transfer format ................. 65 figure 12- service arbitration hierarchy ...................................... 67 figure 13- queue linked list structure .......................................... 68 figure 14- traffic shaping on the wan port .................................. 72 figure 15- non-integer shpincr ........................................................... 73 figure 16- thresholds and count definitions ............................... 77 figure 17- epd/ppd congestion discard rules .............................. 80 figure 18 - cell congestion discard rules .................................... 81 figure 19 - fcq discard rules .............................................................. 82 figure 20- 1 bank configuration for 1mb of zbt ssram ............. 86 figure 21- 1 bank of 1mb of late write ssram (2 x 256k*18) ........ 87 figure 22- 1 bank of 1mb of late write ssram (1 x 256k*36) ........ 87
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use viii figure 23- 2 bank configuration for 2mb of zbt ssram ............. 88 figure 24- 2 bank configuration for 2mb of late write ssram 89 figure 25- cell storage map ................................................................. 90 figure 26- 4 mb ? 64k cells ...................................................................... 91 figure 27- 8 mb ? 128k cells .................................................................... 91 figure 28- 16 mb ? 256k cells .................................................................. 92 figure 29- context location ............................................................... 153 figure 30- input observation cell (in_cell) .................................. 187 figure 31- output cell (out_cell) .................................................... 188 figure 32- bi-directional cell (io_cell) .......................................... 188 figure 33- layout of output enable and bidirectional cells 189 figure 34- single word read and write ......................................... 191 figure 35- burst read and write ....................................................... 192 figure 36- consecutive write accesses using wrdoneb ........ 193 figure 37- read timing ........................................................................... 194 figure 38- write timing .......................................................................... 194 figure 39- refresh .................................................................................. 195 figure 40- power up and initialization sequence ....................... 195 figure 41- read followed by write timing .................................... 196 figure 42- read followed by write timing .................................... 197 figure 43- utopia l2 transmit slave (loop & wan) ....................... 198 figure 44- utopia l1 receive master (loop & wan) ...................... 198 figure 45- utopia l2 receive master (loop & wan) ...................... 199 figure 46- any-phy receive master (loop & wan) ......................... 200
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use ix figure 47- utopia l2 receive slave (loop & wan) .......................... 201 figure 48- wan utopia l1 transmit master .................................... 201 figure 49- loop utopia l1 transmit master ................................... 202 figure 50- wan utopia l2 transmit master .................................... 202 figure 51- loop utopia l2 transmit master ................................... 203 figure 52- wan any-phy transmit master ....................................... 203 figure 53- loop any-phy transmit master ...................................... 204 figure 54- rstb timing ............................................................................ 208 figure 55- synchronous i/o timing ................................................... 209 figure 56- jtag port interface timing ............................................ 213 figure 57- mechanical drawing 352 pin ball grid array (sbga) 216
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use x list of tables table 1 - terminology ............................................................................ 1 table 2 - sample feature set as a function of memory capacity ..................................................................................... 15 table 3 - pin type definition ............................................................... 17 table 4 - number of ports supported, receive interface .... 51 table 5 - number of ports supported, transmit interface.. 54 table 6 - example wirr transmission sequence ........................ 57 table 7 - available queuing procedures ...................................... 69 table 8 - oam & rrm cell identification ......................................... 74 table 9 - congestion error flags .................................................. 78 table 10 - congestion discard rules selection ......................... 79 table 11 - statistical counts .............................................................. 83 table 12 - in/out bound clp state for statistical counts ....... 84 table 13 - congestion rule & count summary .............................. 84 table 14 - receive interface throughput, mcells/sec ............. 94 table 15 - queue engine throughput, mcells/sec....................... 95 table 16 - transmit interface throughput, mcells/sec ........... 95 table 17 - external queue context memory map....................... 154 table 18 - internal queue context memory map........................ 154 table 19 - internal wan port scheduler context memory map 155 table 20 - internal loop port scheduler context memory map 155 table 21 - 2 bit logarithmic, 2 bit fractional .............................. 156
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xi table 22 - 4 bit logarithmic, 2 bit fractional .............................. 156 table 23 - 4 bit logarithmic, 4 bit fractional .............................. 156 table 24 - vc context record structure .................................... 157 table 25 - vc statistics record structure ................................. 163 table 26 - vc address map record structure ........................... 164 table 27 - port threshold context record structure ........ 166 table 28 - port count context record structure.................. 167 table 29 - class scheduler record structure ........................ 169 table 30 - class context record structure ............................. 172 table 31 - shape txslot context record structure .............. 174 table 32 - shape rate context record structure................... 175 table 33 - cell context record structure ................................ 176 table 34 - free count context structure .................................. 177 table 35 - overall count context structure............................ 177 table 36 - congestion discard context structure ................ 178 table 37 - maximum congestion id context structure........... 179 table 38 - misc error context structure................................... 179 table 39 - wan transmit port polling weight ............................ 180 table 40 - wan poll weight format ................................................. 181 table 41 - wan class status ............................................................... 181 table 42 - loop transmit port polling sequence ..................... 182 table 43 - loop transmit port polling weight........................... 183 table 44 - loop class status ............................................................. 184 table 45 - instruction register ....................................................... 186
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xii table 46 - identification register ................................................... 186 table 47 - boundary scan register ................................................ 186 table 48 - absolute maximum ratings ............................................. 205 table 49 - d.c. characteristics......................................................... 206 table 50 - rtsb timing............................................................................ 208 table 51 - sysclk timing ....................................................................... 209 table 52 - cell buffer sdram interface........................................ 209 table 53 - context memory zbt & late write ssram interface 209 table 54 - microprocessor interface ........................................... 210 table 55 - loop any-phy transmit interface ................................ 210 table 56 - wan any-phy transmit interface ...................................211 table 57 - loop any-phy receive interface....................................211 table 58 - wan any-phy receive interface .................................... 212 table 59 - jtag port interface .......................................................... 213
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 1 1 definitions table 1 - terminology term definition aal5 atm adaptation layer abr available bit rate any-phy interoperable version of utopia and sci-phy, with inband addressing. atm asynchronous transfer mode bom beginning of message cbi common bus interface cbr constant bit rate cdv cell delay variation cdvt cell delay variation tolerance ces circuit emulation service clp cell loss priority com continuation of message cos class of service ctd cell transfer delay dll delay locked loop dsl digital subscriber loop dslam dsl access multiplexer duplex pmc utopia deserializer eci egress connection identifier efci early forward congestion indicator eom end of message epd early packet discard fifo first-in-first-out gcra generic cell rate algorithm gfr guaranteed frame rate
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 2 ibt intrinsic burst tolerance ici ingress connection identifier mbs maximum burst size mcr minimum cell rate oam operation, administration and maintenance pcr peak cell rate pdu packet data unit phy physical layer device ppd partial packet discard pti payload type indicator qos quality of service qrt pmc?s traffic management device qse pmc?s switch fabric device rrm reserved or resource management sar segmentation and re-assembly sci-phy pmc-sierra enhanced utopia bus scr sustained cell rate s/uni-atlas pmc?s oam and address resolution device ubr unspecified bit rate utopia universal test & operations phy interface for atm vbr variable bit rate vcc virtual channel connection vortex pmc utopia/any-phy slave serializer vpc virtual path connection wan wide area network wirr weighted interleaved round robin wrr weighted round robin zbt zero bus turnaround
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 3 2 features ? monolithic single chip atm traffic manager providing vc queuing/shaping and vc, class of service(cos), and port scheduling, congestion management, and switching across 128 ports. ? targeted at systems where many low speed atm data ports are multiplexed onto few high speed ports. ? 869 kcells/s non shaped throughput in full duplex. ? 1.73 mcells/s non shaped throughput in half duplex. ? 1.42 mcells/s shaped throughput (aggregate of the four shapers). ? supports four wan uplink ports, with port aliasing. ? supports 128 loop ports. loop port can support an uncongested rate up to 230kcells/sec. ? provides 4 classes of service per port with configurable traffic parameters enabling support for a mix of cbr, vbr, gfr, and ubr classes. ? provides 1024 per-vc queues individually assignable to any cos in any port. ? provides support of up to 256k cells of shared buffer. ? provides 2 independent cell emission schedulers, 1 for the wan ports, and 1 for the loop ports. the schedulers have the following features: three level hierarchical cell emission scheduling at the port, class, and vc levels. ? wan port scheduling: ? weighted interleaved round robin wan port scheduling. ? per port priority fair queued class scheduling with port independence. ? per class: ? weighted fair queued vc scheduling with class independence or,
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 4 ? shaped fair queued vc scheduling applying rate based per vc shaping or, ? frame continuous queued vc scheduling for vc merge and packet re-assembly. ? loop port scheduling: ? weighted interleaved round robin loop port scheduling. ? per port priority fair queued class scheduling with port independence. ? per class: ? weighted fair queued vc scheduling with class independence or, ? frame continuous queued scheduling for vc merge and packet re-assembly. ? congestion control applied per-vc, per-class, per-port and per-direction. ? flexible, progressive hierarchical throttling of buffer consumption. provides sharing of resources during low congestion, memory reservation during high congestion. ? applies epd and ppd on a per-vc, per-class, per-port, and per-direction basis with clp differentiation, following emerging gfr standards. ? provides efci marking on a per vc basis. ? provides interrupts and indication of most recent vc/class/port that exceeded maximum thresholds. ? provides flexible vpc or vcc switching selectable on a per vc basis as follows: ? any wan port to any wan port. ? any wan port to any loop port. ? any loop port to any wan port. ? any loop port to any loop port.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 5 ? microprocessor port to any loop or wan port. ? any loop or wan port to microprocessor port. ? vp termination (in conjunction with the s/uni-atlas). ? vpi or vpi/vci header mapping. ? vc merge. ? provides flexible signaling and control capabilities: ? provides 4 independent up transmit queues. ? provides simultaneous aal5 sar assistance for traffic to/from the up on up to 1024 vcs. ? supports up cell injection into any queue. ? provides per vc selectable oam cell pass through or switching to microprocessor port. ? supports crc10 calculation for oam cells destined for/originating from the microprocessor. ? diagnostic access provided to context memory and cell buffer memory via the microprocessor. ? provides per vc clp0/1 transmit counts. ? provide global per clp0/1 discard counts. ? provides various error statistics accumulation. ? determines the ingress connection identifier from one of several locations: the cell prepend, the vpi/vci field, or the hec/udf field. ? interface support: ? provides a 8/16-bit any-phy compliant master/slave loop side interface supporting up to 128 ports (logical phys). ? provides an 8/16-bit any-phy compliant master/slave wan side interface supporting up to 4 ports (phys).
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 6 ? provides a 32-bit multiplexed microprocessor bus interface for signaling, control, and cell message extraction and insertion, context memory access, control and status monitoring, and configuration of the ic. ? provides a 32-bit sdram interface for cell buffering. ? provides a 36-bit pipelined zbt or register to register late write ssram interface for context storage. ? packaging: ? provides a standard 5 signal p1149.1 jtag test port for boundary scan board test purposes. ? implemented in low power, 0.25 micron, +2.5/3.3v cmos technology with cmos compatible inputs and outputs. ? 352-pin high-performance ball grid array (sbga) package.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 7 3 applications ? mini-dsl access multiplexers (mini-dslams). ? subscriber access terminal devices. ? apon customer located subscriber access equipment ? lmds customer located subscriber access equipment. ? integrated access devices. figure 1 shows the s/uni-apex-1k800 in a mini-dslam application. the s/uni-apex-1k800 acts as a cell buffer and traffic manager. the s/uni-atlas- 1k800 provides address resolution and policing. the mini-dslam application supports eight liu devices per line card. each xdsl modem is connected by its utopia port to a fpga which provides an interface to the anyphy bus. if hot swap capability is needed the bus signals need to be passed through switching or tristate drivers to isolate the card when being plugged in. the fpga performs the task of interfacing several 31 logical port utopia bus signals to the single 128 logical port any-phy bus supported by the s/uni- apex-1k800. figure 1 - s/uni-apex-1k800 in oc3 mini-dslam application dsl phy up to 31 utopia l2 ports s/uni- duplex dsl phy line cards s/uni- apex- 1k800 s/uni- atlas- 1k800 phy core card host cpu anyphy/ sciphy context ssram packet/cell sdram ingress ssram egress ssram s/uni- vortex dsl phy up to 31 utopia l2 ports s/uni- duplex dsl phy line cards up to 8 lvds links to s/uni-duplex devices per s/uni-vortex 200mbps lvds
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 8 4 references 1. pmc-sierra; ?saturn compatible interface for atm phy layer and atm layer devices, level 2?; pmc-940212; dec. 8, 1995. 2. pmc-sierra; dslam engineering document. 3. ?traffic management and switching with the vortex chip set: s/uni-apex technical overview?, pmc-981024. 4. atm forum, ?universal test & operations phy interface for atm (utopia), level 2?, version 1.0, af-phy-0039.000, june 1995. 5. itu-t recommendation i.432.1, ?b-isdn user-network interface ? physical layer specification: general characteristics?, 08/96. 6. itu-t recommendation i.363, ?b-isdn atm adaptation layer (aal) specification?, march 1993. 7. af traffic management specification version 4.1 af-tm-0121.000, march 1999. 8. af traffic management baseline text document btd-tm-01.01, april 1998. 9. i.610 oam. 10. pmc sierra, ?saturn interface specification and interoperability framework for packet and cell transfer between physical layer and link layer devices?, pmc980902. 11. pmc sierra, ?s/uni apex h/w programmer?s guide?, pmc-991454.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 9 5 application examples please refer to the document ?traffic management and switching with the vortex chip set: s/uni-apex technical overview?, pmc-981024.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 10 6 block diagram figure 2 shows the function block diagram of the s/uni-apex-1k800 atm traffic manager. the functional diagram is arranged such that cell traffic flows through the s/uni-apex-1k800 from left to right.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 11 figure 2 - s/uni-apex-1k800 block diagram with datapath loop rx any-phy wan rx any-phy fifo 4 cell ici select sdram i/f queue engine loop tx any-phy wan tx any-phy fifo 4 cell uproc i/f ssram i/f loop port scheduler jtag lrclk lrpa lrsx lrsop lrdat[15:0] lrprty lrenb lradr[5:0] ltadr[7:0] ltpa ltenb ltsx ltsop ltdat[15:0] ltprty ltclk cell data path context data path sar assist wan port scheduler wrclk wrpa wrsx wrsop wrdat[15:0] wrprty wrenb wraddr[2:0] tdo tdi tck tms trstb wtadr[2:0] wtpa wtenb wtsx wtsop wtdat[15:0] wtprty wtclk c b c s b c b r a s b c b c a s b c b r w e b c b a [ 1 1 : 0 ] c b b s [ 1 : 0 ] c b d q m [ 1 : 0 ] c b d q [ 3 1 : 0 ] cmd[33:0] cmp[1:0] cma[18:0] cmrwb cmceb cmab[18:17] ici select fifo 4 chan 2 cell fifo 2 cell fifo 4 cell fifo 4 chan 4 cell bclk csb wr ad[31:0] adsb burstb blast readyb wrdoneb inthib intlob buspol sysclk rstb oe
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 12 7 description the PM7329 s/uni-apex-1k800 is a full duplex atm traffic management device, providing cell switching, per vc queuing, traffic shaping, congestion management, and hierarchical scheduling to up to 128 loop ports and up to 4 wan ports. the s/uni-apex-1k800 provides per-vc queuing for 1024 vcs. a per-vc queue may be allocated to any class of service (cos), within any port, in either direction (ingress or egress path). per-vc queuing enables pcr or scr per-vc shaping on wan ports and greater fairness of bandwidth allocation between vcs within a cos. the s/uni-apex-1k800 provides three level hierarchical scheduling for port, cos, and vc level scheduling. there are two, three level schedulers; one for the loop ports and one for the wan ports. the three level scheduler for the wan ports provides: ? weighted interleaved round robin (wirr) scheduling across the 4 wan ports enabling selectability of bandwidth allocation between the ports. ? priority fair scheduling across the 4 cos?s within each port. this class scheduler is a modified priority scheduler allowing minimum bandwidth allocations to lower priority classes within the port. class scheduling within a port is independent of activity on all other ports. ? there are three types of vc schedulers. vc scheduling within a class is independent of activity on all other classes ? shaped fair queuing is available for 4 classes. if the cos is shaped, each vc within the class is scheduled for emission based on its vcs shaping rate. during class congestion, the vc scheduler may lower a vcs rate in proportion to a normalization factor calculated as a function of the vcs rate and the aggregate rate of all active vcs within the class. ? weighted fair queuing in which weights are used to provide fairness between the vcs within a class. ? frame continuous scheduling where an entire packet is accumulated prior to transferring to a class queue. the three-level scheduler for the loop ports provides: ? weighted interleaved round robin (wirr) scheduling across the 128 loop ports enabling selectability of bandwidth allocation between the ports
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 13 and ensuring minimal phy layer fifoing is required to support a wide range of port bandwidths. ? priority scheduling across the 4 cos?s within each port. class scheduling within a port is independent of activity on all other ports. ? vcs within a class are scheduled with a weighted fair queue (wfq) scheduler or frame continuous scheduling. vc scheduling within a class is independent of activity on all other classes. shaping is not supported on loop ports. the s/uni-apex-1k800 forwards cells via tail of queue enqueuing and head of queue dequeuing (emission) where tail of queue enqueuing is controlled by the vc context record and subject to congestion control, and head of queue dequeuing is controlled by the three-level hierarchical schedulers. the vc context record allows for enqueuing to any queue associated with any port, thus full switching is supported, any port to any port. the s/uni-apex-1k800 supports up to 256k cells of shared buffering in a 32-bit wide sdram. memory protection is provided via an inband crc on a cell-by-cell basis. buffering is shared across direction, port, class, and vc levels. the congestion control mechanism provides guaranteed resources to all active vcs, allows sharing of available resources to vcs with excess bandwidth, and restricts buffer allocation on a per-vc, per-class, per-port, and per-direction basis. the congestion control mechanism supports ppd and epd on a clp0 and clp1 basis across per-vc, per-class, per-port, and per-direction structures. efci marking is supported on a per-vc basis. congestion thresholds and packet awareness is selectable on a per connection basis. the s/uni-apex-1k800 provides flexible capabilities for signaling, management, and control traffic. there are 4 independent up receive queues to which both cell and aal5 frame traffic may be en-queued for termination by the up. a staging buffer is also provided enabling the up to en-queue both cell and aal5 frame traffic to any outgoing queue. aal5 sar assistance is provided for aal5 frame traffic to and from the up. aal5 sar assistance includes the generation and checking of the 32-bit crc field and the ability to reassemble all the cells from a frame in the vc queue prior to placement on the up queues. any or all of the 1024 vcs may be configured to be routed to/from the up port. any or all of the vcs configured to be routed to/from the up port may also be configured for aal5 sar assistance simultaneously. oam cells may optionally (per-vc selectable) be routed to a up receive queue or switched with the user traffic. crc10 generation and checking is optionally provided on oam cells to/from the up. the s/uni-apex-1k800 maintains cell counts of clp0 and clp1 cell transmits on a per-vc basis. global clp0 and clp1 congestion discards are also
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 14 maintained. various error monitoring conditions and statistics are accumulated or flagged. the up has access to both internal s/uni-apex-1k800 registers and the context memory as well as diagnostic access to the cell buffer memory. the s/uni-apex-1k800 provides a 8/16-bit any-phy compliant loop side master/slave interface supporting up to 128 ports. egress cell transfers across the interface are identified via an inband port identifier prepended to the cell. the slave devices must match the inband port identifier with their own port id or port id range in order to accept the cell. per port egress flow control is effected via a 8-bit address polling bus to which the appropriate slave device responds with out of band per port flow control status. ingress cell transfers across the interface are effected via a combination of utopia l2 flow control polling and device selection for up to 32 slave devices. the any-phy loop side interface may be reconfigured as a standard single port utopia l2 compliant slave interface. 16- bit prepends are optionally supported on both ingress and egress for cell flow identification enabling use with external address resolution devices, switch fabric interfaces, or other layer devices. the s/uni-apex-1k800 provides an 8/16-bit any-phy or utopia l2 compliant wan side master/slave interface supporting up to 4 ports. 16-bit prepends are optionally supported on both ingress and egress for cell flow identification enabling use with external address resolution devices, switch fabric interfaces, or other layer devices. the wan port has port aliasing on the egress, providing in service re-direction without requiring re-programming the context of active vcs. the s/uni-apex-1k800 provides a 32-bit microprocessor bus interface for signaling, control, cell and frame message extraction and insertion, vc. class and port context access, control and status monitoring, and configuration of the ic. microprocessor burst access for registers, cell and frame traffic is supported. the s/uni-apex-1k800 provides a 36-bit zbt or late write ssram interface for context storage supporting up to 4mb of context for up to 1024 vcs and up to 256k cell buffer pointer storage. context memory protection is provided via 2 bits of parity over each 34-bit word. the total number of cells, the total number of vcs, support for address mapping and shaped fair queuing is limited to the amount of context and cell buffer memory available. below is a table illustrating the most common combinations of memory/features.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 15 table 2 - sample feature set as a function of memory capacity context memory size ssram cell buffer memory size sdram # vc # cell buffers address mapping support shaping support 1 mb 4mb 1024 64 k yes no 2 mb 4mb 1024 64 k yes yes 2 mb 16mb 1024 256 k yes yes the s/uni-apex-1k800 provides facilities to enable sparing capability with another s/uni-apex-1k800 device. the facilities enable a 'warm standby' capability in which connection setup between the two devices can be maintained identically but some cell loss will occur at the point of device swapping. the facilities do not include a cell by cell lock step between the two s/uni-apex- 1k800 devices. to avoid any cell replication, queues in the 'spare' s/uni-apex- 1k800 will be kept empty, thus causing all queued traffic in the 'active' s/uni- apex-1k800 to be lost at the point of switch over. however, since connection setup is maintained identically between the two s/uni-apex-1k800 devices, switch over can happen instantaneously, thus avoiding any connection timeout or tear down issues. the s/uni-apex-1k800 facilities provided are the disable and filter control bits in the receive and transmit control register. these control bits are asserted in the spare s/uni-apex-1k800 to ensure the queues remain empty until swapping is initiated. alternatively, asserting only the filter enable bits allow signaling and control traffic continuity to be maintained to the spare s/uni-apex- 1k800 to enable datapath integrity testing on the spare plane and to ensure control communications paths to the spare plane are usable.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 16 8 pin diagram the s/uni-apex-1k800 is packaged in a 352-pin ball grid array (sbga) package having a body size of 35 mm by 35 mm. figure 3 - s/uni-apex-1k800 bottom view pin out 2625242322212019181716151413121110987654321 a vss5 vss4 cmd [0] cmd [4] cmd [7] cmd [11] cmd [14] cmd [18] cmd [21] pch cmd [27] cmd [30] vss3 vss2 ad [2] ad [4] pch ad [10] ad [13] ad [17] ad [20] ad [24] ad [27] ad [31] vss1 vss0 a b vss9 vdd10 vss8 cmd [1] cmd [5] cmd [8] cmd [12] cmd [15] cmd [19] cmd [23] cmd [25] cmd [29] cmd [32] cmd [33] sysclk ad [6] ad [8] ad [12] ad [ 16] ad [19] ad [23] ad [26] ad [30] vss7 vdd9 vss6 b c cmrwb vss11 vdd12 cmp [1] cmd [2] cmd [6] cmd [9] cmd [13] cmd [16] cmd [20] cmd [24] cmd [28] cmd [31] ad [0] ad [3] ad [7] ad [11] ad [15] ad [ 18] ad [22] ad [25] ad [29] inthib vdd11 vss10 bclk c d cmab [1] cmceb cmp [0] vdd17 nc cmd [3] pch cmd [10] vdd16 cmd [17] cmd [22] cmd [26] vdd15 ad [1] ad [5] ad [9] ad [14] vdd14 ad [21] pch ad [28] n c vd d13 intlob wrdoneb blast d e cma [16] cma [17] cma [19] nc buspo l bterm b burstb c sb e f cma [12] cma [15] cmab [0] cma [18] readyb wr adsb lradr [2] f g cma [9] cma [11] cma [14] pch pch lradr [0] lradr [3] lradr [5] g h cma [5] cma [8] cma [10] cma [13] lradr [1] lradr [4] lrenb lrprty h j cma [2] cma [4] cma [7] vdd18 v d d 1 9 lrpa lrso p lrd a t [ 0 ] j k pch cma [0] cma [3] cma [6] lrc lk lrsx lrd a t [ 1 ] lrd a t [ 3 ] k l ltdat [12] ltdat [14] ltdat [15] cma [1] pch lrdat [2] lrdat [4] lrdat [6] l m ltd a t [ 9 ] ltd a t [ 1 0 ] ltd a t [ 1 1 ] ltd a t [ 1 3 ] lrdat [5] lrdat [7] lrdat [8] lrdat [9] m n v ss1 3 ltd a t [ 6 ] ltd a t [ 7 ] ltd a t [ 8 ] vd d 20 lrdat [10] lrdat [ 11] vss12 n p v ss1 5 ltd a t [ 5 ] ltd a t [ 4 ] v d d 2 1 lrdat [14] lrdat [13] lrdat [ 12] vss14 p r ltd a t [ 3 ] ltd a t [ 2 ] ltd a t [ 1 ] ltpa pc h wradr [1] wradr [0] lrd a t [ 1 5 ] r t ltd a t [ 0] ltc lk lten b ltso p wrsop wrclk wrenb wradr [2] t u pch ltsx ltadr [11] ltadr [8] wrdat [3] wrdat [0] wrprty wrpa u v ltprty lta d r [ 10 ] lta d r [ 7 ] v d d 2 3 vdd22 wrdat [4] wrdat [1] wrsx v w ltadr [9] ltadr [6] ltadr [4] ltadr [1] pch wrdat [7] wrdat [5] wrdat [2] w y ltadr [5] ltadr [3] ltadr [0] wtdat [14] wrdat [ 13] wrdat [10] wrdat [8] wrdat [6] y aa lta d r [ 2 ] wtdat [15] wtdat [13] wtdat [10] rstb wrdat [14] wrdat [11] wrdat [9] aa ab pc h wtdat [12] wtdat [9] nc nc tdi wrdat [15] wrdat [12] ab ac wtdat [11] wtdat [8] wtdat [6] vdd4 scanmb wtdat [2] wtenb wtsop vdd3 cba [9] cba [4] cba [0] cbcasb vdd2 cbdq [26] cbdq [22] cbdq [17] vdd1 cbdq [10] cbdq [7] cbdq [3] nc vdd0 trstb tms oe ac ad w tda t [ 7 ] v ss1 7 v d d 6 sc a nen w tda t [ 3] wtpa wtc lk w ta dr [ 1] c ba [ 10 ] c ba [ 6] c ba [ 2] c bbs [ 0] c bweb cbdq [31] cbdq [28] cbdq [24] cbdq [20] cbdq [16] cbdq [13] cbdq [9] cbdq [6] cbdq [2] tdo vdd5 vss16 tck ad ae vss21 vdd8 vss19 wtdat [4] wtdat [0] wtsx wtadr [0] cba [11] cba [7] cba [3] cba [1] cbcsb cbdqm [1] cbdqm [0] cbdq [29] cbdq [25] cbdq [23] cbdq [19] cbdq [15] cbdq [12] cbdq [8] cbdq [5] cbdq [1] vss20 vdd7 vss18 ae af v ss2 7 v ss2 6 w tda t [ 5 ] w tda t [ 1 ] pc h w tprty w ta dr [ 2] c ba [ 8] c ba [ 5] pc h c bbs [ 1] c bra sb v ss25 v ss24 cbdq [30] cbdq [27] pc h cbdq [21] cbdq [18] cbdq [14] cbdq [11] pc h c bdq [ 4 ] c bdq [ 0 ] v ss23 v ss22 af 2625242322212019181716151413121110987654321
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 17 9 pin description notes on pin description: 1. all s/uni-apex-1k800 inputs and bi-directionals present minimum capacitative loading 2. lvcmos, lvttl compatible logic levels. 3. all pins are 5v tolerant. 4. inputs rstb, oe, tms, tdi and trstb have internal pull-up resistors. 5. the recommended power supply sequencing is as follows: 3.1 vdd power must be supplied either before or simultaneously with pch. 3.2 the vdd power must be applied before input pins are driven or the input current per pin must be limited to less than the maximum dc input current specification. (20 ma) 3.3 power down the device in the reverse sequence. table 3 - pin type definition type definition input input output pin is always driven tri-state pin is either driven, or held in hi-z bidi bidirectional od open drain. either driven low or held in hi-z. 9.1 loop any-phy receive master/transmit slave interface (28 signals) pin name type pin no. function lrclk input k4 loop receive clock. lrclk is used to transfer data blocks in the receive directions across the any- phy interface. lrclk must cycle at a 52 mhz or lower instantaneous rate.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 18 pin name type pin no. function lrpa input (master) tri-state (slave) j3 loop receive packet available. lrpa indicates whether at least one cell is queued for transfer in the selected phy device. this pin is in hi-z when the loop receive interface is not enabled. if receive master mode is selected, this signal is an input. the selected phy device drives lrpa with the cell availability status n lrclk cycles after lradr[5:0] matches the phy device address. if the phy device is a utopia device, n=1. if the phy device is an any-phy device, n=2. assertion of lrpa indicates that at least one entire cell is available. if transmit slave mode is selected, this signal is a tri- state output. the s/uni-apex-1k800 drives lrpa high 1 lrclk after lradr[5:0] matches the programmed looprxslaveaddr register. a logical high indicates that the s/uni-apex-1k800 is capable of accepting at least one cell. lrpa is sampled/updated/hi-z?d on the rising edge of lrclk.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 19 pin name type pin no. function lrenb input (slave) output (master) h2 loop receive enable. the active low receive enable (lrenb) signal is used to initiate the transfer of a data block from the selected physical layer device to the s/uni-apex-1k800. this pin is in hi-z when the loop receive interface is not enabled. if receive master mode is selected, this signal is an output and the start of block transfer must occur 1 or 2 lrclk cycles after device selection occurs. if the phy device is a utopia device, n=1. if the phy device is an any-phy device, n=2. device selection occurs when the selected device address is placed on lradr[5:0] with lrenb held high followed by lrenb low in the next lrclk period. lrenb is held low for m cycles where m is the number of 8 or 16-bit words in the block transfer. if transmit slave mode is selected, this signal is an input and lrdat[15:0] word is accepted coincident with lrenb being sampled. lrenb is sampled/updated on the rising edge of lrclk.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 20 pin name type pin no. function lradr[0] .. lradr[5] input (slave) output (master) g3 h4 f1 g2 h3 g1 loop receive address. the lradr[5:0] signals are used to address up to thirty two physical layer devices for the purposes of polling and device selection. this pin is in hi-z when the loop receive interface is not enabled. if ul2 or any-phy receive master mode is selected, these signals are outputs. lradr[5:0] selects a device for polling by applying the device address n lrclk cycles prior to sampling lrpa. if the phy device is a utopia device, n=1. if the phy device is an any-phy device, n=2. lradr will insert 1 null address between address changes. if ul1 master mode is selected, this bus is driven to a high null address. lradr[5:0] selects a device to transfer a data block when the lrenb is last sampled high. the start of data block transfer must occur 1 or 2 lrclk cycles after device selection occurs. lradr[5:0] = 3f hex is used as the null address. no phy device can match the null address. if transmit slave mode is selected, these signals are inputs. the s/uni drives the lrpa 1 lrclk after the lradr[4:0] matches the programmed looprxslaveaddr register, and lradr[5] is zero. lradr[5:0] is sampled/updated or on the rising edge of lrclk. lrsx input k3 loop receive start of transfer. lrsx is asserted by the selected phy device during the first cycle of a data block transfer coinciding with the port address prepend. required only during any-phy mode. for utopia modes, this signal should be tied low. lrsx is sampled on the rising edge of lrclk.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 21 pin name type pin no. function lrsop input j2 loop receive start of packet . lrsop marks the start of the cell on the lrdat[15:0] bus. when lrsop is high, the first data word of the cell is present on the lrdat[15:0] stream. if the selected device is an any-phy device, the lrsop cycle will be preceded by the lrsx cycle marking the any- phy port address transfer cycle. lrsop considered valid only when the lrenb signal is low. lrsop becomes high impedance upon sampling lrenb high or if no physical layer device was selected for transfer. lrsop is sampled on the rising edge of lrclk. lrdat[0] .. lrdat[15] input j1 k2 l3 k1 l2 m4 l1 m3 m2 m1 n3 n2 p2 p3 p4 r1 loop receive data. lrdat[15:0] carries the transfer block words that have been read from the physical layer device to the s/uni-apex-1k800 internal cell buffers. lrdat bus is considered valid only when the lrenb signal was low n cycles previous. lrdat is expected to become high impedance n lrclk cycles after sampling lrenb high or upon completion of a data block transfer. if the phy device is a utopia device, n=1. if the phy device is an any-phy device, n=2. all 16 bits are used in 16-bit mode. in 8 bit mode, lrdat[15:8] should either be tied high or low, as only the first 8 bits ltdat[7:0] are valid. lrdat[15:0] is sampled on the rising edge of lrclk.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 22 pin name type pin no. function lrprty input h1 loop receive parity. lrprty provides programmable odd/even parity of the lrdat[15:0] bus. lrprty is considered valid only when the lrenb signal was low n cycles previous. if the phy device is a utopia device, n=1. if the phy device is an any-phy device, n=2. lrprty is expected to become high impedance n lrclk cycles after sampling lrenb high. a parity error is indicated by a status bit and a maskable interrupt. lrprty is sampled on the rising edge of lrclk. 9.2 loop any-phy transmit master/receive slave interface (34 signals) pin name type pin no. function ltclk input t25 loop transmit clock. ltclk is used to transfer data blocks in the transmit direction across the any- phy interface. ltclk must cycle at a 52 mhz or lower instantaneous rate.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 23 pin name type pin no. function ltadr[0] .. ltadr[11] output (master) input (slave) y24 w23 aa26 y25 w24 y26 w25 v24 u23 w26 v25 u24 loop transmit address. the ltadr[7:0] signals are used to address up to 128 logical channels for the purposes of polling on the ltpa signal. 1 or more phy devices can share the ltpa signal. this pin is in hi-z when the loop transmit interface is not enabled. if transmit master mode is selected, these signals are outputs. ltadr[7:0] selects a logical channel for polling by applying the logical channel address n ltclk cycles prior to sampling ltpa. if the phy device is a utopia device, n=1. if the phy device is an any-phy device, n=2. ltadr inserts null cycles between addresses. for any-phy transmit master, ltadr [6 :0] corresponds to the portid[6:0] fields in the any- phy address word prepend format . for utopia l2 transmit master, ltadr[4:0] is also used to select a utopia device to transfer a cell to, when ltenb is last sampled high. ? ltadr[11:5] should be left unconnected. for utopia l1 transmit master, ltadr[11:0] are unused and should be left unconnected. if utopia l2 receive slave mode is selected, these signals are inputs. the s/uni-apex-1k800 drives ltpa high 1 ltclk after the ltadr[4:0] matches the programmed looptxslaveaddr register. ? ltadr[11:5] are unused and should be tied either high or low. ? ltadr[7:0] is sampled/updated on the rising edge of ltclk.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 24 pin name type pin no. function ltpa input (master) tri-state (slave) r23 loop transmit packet available. ltpa indicates the availability of space in the selected polled port when polled using the ltadr[7:0] signals. this pin is in hi-z when the loop transmit interface is not enabled. if transmit master mode is selected, this signal is an input. the phy device whose address or address range matches ltadr[7:0] drives the ltpa signal with the transmit fifo availability status of the selected logical channel n ltclk cycles after the match. if the phy device is a utopia device, n=1. if the phy device is an any-phy device, n=2. assertion of ltpa indicates that at least k entire cell buffer is available in that logical channel. k = 1 if the register looptxtwocellen = 0. k = 2 if the register looptxtwocellen = 1. if receive slave mode is selected, this signal is a tri- state output. the s/uni-apex-1k800 drives ltpa 1 ltclk after ltadr[4:0] matches the programmed looptxslaveaddr register. a logical high indicates that at least one cell is available for transmission. ltpa is sampled/updated/hi-z?d on the rising edge of ltclk. ltenb output (master) input (slave) t24 loop transmit enable. ltenb indicates cell transfers to utopia and sci-phy devices. the device is selected via a match on ltadr[6:0] when ltenb is last sampled high. this pin is in hi-z when the loop transmit interface is not enabled. if transmit master mode is selected, this signal is an output. ltenb is held low for the duration of the cell transfer. if receive slave mode is selected, this signal is an input. ltenb is sampled/updated on the rising edge of ltclk.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 25 pin name type pin no. function ltsx output u25 loop transmit start of transfer. ltsx is asserted by the s/uni-apex-1k800 during the first cycle of a data block transfer. ltsx assertion will coincide with the port address prepend, if the cell being transferred has a prepended port address. required only during any-phy mode. should be left unconnected during utopia modes. ltsx is updated on the rising edge of ltclk. ltsop output (master) tri-state (slave) t23 loop transmit start of cell. ltsop marks the start of cell on the ltdat[15:0] data bus. ltsop is driven high when the first word of the cell (excluding address prepend) is present on the ltdat[15:0] stream. ltsop is asserted for each cell. in transmit master mode, the signal is always driven. in receive slave mode, this signal is driven 1 ltclk after ltenb is asserted. ltsop is updated/hi-z?d on the rising edge of ltclk. ltdat[0] .. ltdat[15] output (master) tri-state (slave) t26 r24 r25 r26 p24 p25 n25 n24 n23 m26 m25 m24 l26 m23 l25 l24 loop transmit data. ltdat[15:0] carries the data block transfers to the physical layer devices. in 8 bit mode, only ltdat[7:0] are valid. in transmit master mode, the entire bus is always driven. in receive slave mode, this bus is driven 1 ltclk after ltenb is asserted. pull up/downs are required for the entire bus, regardless of whether the bus is in 8 or 16 bit mode. ltdat[15:0] is updated/hi-z?d on the rising edge of ltclk.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 26 pin name type pin no. function ltprty output (master) tri-state (slave) v26 loop transmit parity. this signal provides programmable odd/even parity of the ltdat[15:0] bus. in transmit master mode, the signal is always driven. in receive slave mode, this signal is driven 1 ltclk after ltenb is asserted. ltprty is updated/hi-z?d on the rising edge of ltclk. 9.3 wan any-phy receive master/transmit slave interface (25 signals) pin name type pin no. function wrclk input t3 wan receive clock. wrclk is used to transfer data blocks in the receive direction across the any- phy interface. wrclk must cycle at a 52 mhz or lower instantaneous rate.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 27 pin name type pin no. function wrpa input (master) tri-state (slave) u1 wan receive packet available. wrpa indicates cell availability. this pin is in hi-z when the wan receive interface is not enabled. if master mode is selected, the selected phy device drives wrpa with the cell availability status n wrclk cycles after wradr[2:0] matches the phy device address. if the phy device is a utopia device, n=1. if the phy device is an any-phy device, n=2. assertion of wrpa indicates that at least one entire cell is available. if slave mode is selected, this signal is an output and the s/uni-apex-1k800 plays the roll of a single port utopia l2 slave device driving the wrpa when the wradr matches the programmed wanrxslaveaddr register. a logical high indicates that the s/uni-apex-1k800 is capable of accepting at least one cell. wrpa is sampled/updated/hi-z?d on the rising edge of wrclk.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 28 pin name type pin no. function wrenb output (master) input (slave) t2 wan receive enable. the active low receive enable (wrenb) output is used to initiate the transfer of a data block from the selected physical layer device to the s/uni-apex-1k800. this pin is in hi-z when the wan receive interface is not enabled. if master mode is selected, this signal is an output and the start of block transfer must occur 1 or 2 wrclk cycles after device selection occurs. device selection occurs when the selected device address is placed on wradr[2:0] with wrenb held high followed by wrenb low in the next wrclk period. wrenb is held low for m cycles where m is the number of 8 or 16-bit words in the block transfer. if slave mode is selected, this signal is an input and wrdat[15:0] word is accepted coincident with wrenb being sampled. wrenb is sampled/updated on the rising edge of wrclk.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 29 pin name type pin no. function wradr[0] .. wradr[2] output (master) input (slave) r2 r3 t1 wan receive address. the wradr[2:0] signals are used to address up to four physical layer devices for the purposes of polling and device selection. this pin is in hi-z when the wan receive interface is not enabled. if ul2 or any-phy receive master mode is selected, this bus is an output. wradr[2:0] selects a device for polling by applying the device address n wrclk cycles prior to sampling wrpa. if the phy device selected is a utopia device, n=1. if the phy device selected is an any-phy device, n=2. when supporting multiple phys, wradr will insert 1 null address between address changes. if ul1 master mode is selected, this bus is driven to a high null address. wradr[2:0] selects a device to transfer a data block when the wrenb is last sampled high. the start of data block transfer must occur 1 or 2 wrclk cycles after device selection occurs. wradr[2:0] = 7 hex is used as the null address. no phy device can match the null address. if slave mode is selected, this signal is an input and the s/uni-apex-1k800 plays the roll of a single port utopia l2 slave device driving the wrpa 1 wrclk after the wradr[1:0] matches the programmed wanrxslaveaddr register, and wradr[2] is zero. wradr[2:0] is sampled/updated on the rising edge of wrclk. wrsx input v1 wan receive start of transfer. wrsx is asserted by the selected phy device during the first cycle of a data block transfer coinciding with the port address prepend. wrsx is ignored during cell transfers from utopia or sci-phy devices. wrsx is updated on the rising edge of wrclk.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 30 pin name type pin no. function wrsop input t4 wan receive start of packet . wrsop marks the start of the cell on the wrdat[15:0] bus. when wrsop is high, the first data word of the cell is present on the wrdat[15:0] stream. if the selected device is an any-phy device, the wrsop cycle will be preceded by the wrsx cycle marking the any- phy port address transfer cycle. wrsop is considered valid only when the wrenb signal is low. wrsop becomes high impedance upon sampling wrenb high or if no physical layer device was selected for transfer. wrsop is sampled on the rising edge of wrclk. wrdat[0] .. wrdat[15] input u3 v2 w1 u4 v3 w2 y1 w3 y2 aa1 y3 aa2 ab1 y4 aa3 ab2 wan receive data. wrdat[15:0] carries the transfer block words that have been read from the physical layer device to the s/uni-apex-1k800 internal cell buffers. all 16 bits are used in 16-bit mode, only the first 8 bits wrdat[7:0] are valid in 8-bit mode. the wrdat bus is considered valid only when the wrenb signal was low n cycles previous. wrdat is expected to become high impedance n wrclk cycles after sampling wrenb high or upon completion of a data block transfer. if the phy device selected is a utopia device, n=1. if the phy device selected is an any-phy device, n=2. wrdat[15:0] is sampled on the rising edge of wrclk.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 31 pin name type pin no. function wrprty input u2 wan receive parity. wrprty provides programmable odd/even parity of the wrdat[15:0] bus. the wrprty signal is considered valid only when the wrenb signal was low n cycles previous. if the phy device selected is a utopia device, n=1. if the phy device selected is an any-phy device, n=2. wrprty is expected to become high impedance n wrclk cycles after sampling wrenb high. a parity error is indicated by a status bit and a maskable interrupt. wrprty is sampled on the rising edge of wrclk. 9.4 wan any-phy transmit master/receive slave interface (25 signals) pin name type pin no. function wtclk input ad20 wan transmit clock. wtclk is used to transfer data blocks in the transmit direction across the any- phy interface. wtclk must cycle at a 52 mhz or lower instantaneous rate.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 32 pin name type pin no. function wtadr[0] .. wtadr[2] output (master) input (slave) ae20 ad19 af20 wan transmit address. the wtadr[2:0] signals are used to address up to four logical channels for the purposes of polling. this pin is in hi-z when the wan transmit interface is not enabled. if master mode is selected, these signals are outputs. wtadr[2:0] selects a logical channel for polling by applying the logical channel address n wtclk cycles prior to sampling wtpa. if the phy devices are utopia devices, n=1. if the phy devices are any-phy devices, n=2. , wtadr will insert 1 null address between address changes for any-phy transmit master, wtadr[1:0] corresponds to the portid[1:0] fields in the any- phy address word prepend format. wtadr[2:0] = 7 hex is used as the null address. no phy device can match the null address. for utopia l2 transmit master, wtadr[2:0] signals are also used for cell transfer phy selection to utopia compliant phy devices. wtadr[2:0] selects a device to transfer a data block to when the wrenb is last sampled high. for utopia l1 transmit master, wtadr[1:0] contains the value of the wantxslaveaddr register. wtadr[2] is held low. if utopia l2 receive slave mode is selected, these signals are inputs and the s/uni-apex-1k800 plays the roll of a single port utopia l2 slave device driving the wtpa 1 wtclk after the wtadr matches the programmed wantxslaveaddr register. wtadr[2:0] is sampled/updated on the rising edge of wtclk.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 33 pin name type pin no. function wtpa input (master) tri-state (slave) ad21 wan transmit packet available. wtpa indicates cell availability. this pin is in hi-z when the wan transmit interface is not enabled. if master mode is selected, this signal is an input. the phy device whose address or address range matches wtadr[2:0] drives the wtpa signal with the transmit fifo availability status of the selected logical channel n wtclk cycles after the match. if the phy devices are utopia devices, n=1. if the phy devices are any-phy devices, n=2. assertion of wtpa indicates that at least one entire cell buffer is available in that logical channel. if slave mode is selected, this signal is a tri-state output and the s/uni-apex-1k800 plays the roll of a single port utopia l2 slave device driving the wtpa when the wtadr matches the programmed wantxslaveaddr register. a logical high indicates that at least one cell is available for transmission. wtpa is sampled/updated/hi-z?d on the rising edge of wtclk. wtenb output (master) input (slave) ac20 wan transmit enable. wtenb indicates cell transfers to utopia and sci-phy devices. the device is selected via a match on wtadr[2:0] when wtenb is last sampled high. this pin is in hi-z when the wan transmit interface is not enabled. if master mode is selected, this signal is an output. if slave mode is selected, this signal is an input. wtenb is held low for the duration of the cell transfer. wtenb is sampled/updated on the rising edge of wtclk.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 34 pin name type pin no. function wtsx output ae21 wan transmit start of transfer. wtsx is asserted by the s/uni-apex-1k800 during the first cycle of a data block transfer. wtsx assertion will coincide with the port address prepend, if the cell being transferred has a prepended port address. required only during any-phy mode. wtsx is updated on the rising edge of wtclk. wtsop output (master) tri-state (slave) ac19 wan transmit start of packet. wtsop marks the start of cell on the wtdat[15:0] data bus. wtsop is driven high when the first word of the cell (excluding address prepend) is present on the wtdat[15:0] stream. wtsop is asserted for each cell. in transmit master mode, the signal is always driven. in receive slave mode, this signal is driven 1 wtclk after wtenb is asserted. wtsop is updated/hi-z?d on the rising edge of wtclk. wtdat[0] .. wtdat[15] output (master) tri-state (slave) ae22 af23 ac21 ad22 ae23 af24 ac24 ad26 ac25 ab24 aa23 ac26 ab25 aa24 y23 aa25 wan transmit data. wtdat[15:0] carries the data block transfers to the physical layer devices. in 8 bit mode, only wtdat[7:0] are valid. in 8/16bit transmit master mode, the entire bus is always driven. in receive slave mode, this bus is driven 1 wtclk after wtenb is asserted pull up/downs are required for the entire bus, regardless of whether the bus is in 8 or 16 bit mode. wtdat[15:0] is updated/hi-z?d on the rising edge of wtclk.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 35 pin name type pin no. function wtprty output (master) tri-state (slave) af21 wan transmit parity. this signal provides programmable odd/even parity of the wtdat[15:0] bus. in transmit master mode, the signal is always driven. in receive slave mode, this signal is driven 1 wtclk after wtenb is asserted. wtprty is updated/hi-z?d on the rising edge of wtclk.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 36 9.5 context memory synchronous ssram interface (59 signals) pin name type pin no. function cmd[0] .. cmd[33] bidi a24 b23 c22 d21 a23 b22 c21 a22 b21 c20 d19 a21 b20 c19 a20 b19 c18 d17 a19 b18 c17 a18 d16 b17 c16 b16 d15 a16 c15 b15 a15 c14 b14 b13 context memory ssram data. the bi-directional ssram data bus pins interface directly with the synchronous ssram data ports. the s/uni-apex-1k800 presents valid data on the cmd[33:0] pins upon the rising edge of sysclk during write cycles. cmd[33:0] is hi-z?d on the rising edge of sysclk for read cycles. cmd[33:0] is sampled/updated/hi-z?d on the rising edge of sysclk.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 37 pin name type pin no. function cmp[0] .. cmp[1] bidi d24 c23 context memory ssram data parity . the ssram parity pins provide parity protection over the cmd[33:0] data bus. cmp[0] completes the odd parity for cmd[16:0] cmp[1] completes the odd parity for cmd[33:17] cmp[1:0] has the same timing as cmd[33:0]. the cmp[1:0] may be unconnected if parity protection is not required. cmp[1:0] is sampled/updated/hi-z?d on the rising edge of sysclk. cma[0] .. cma[18] output k25 l23 j26 k24 j25 h26 k23 j24 h25 g26 h24 g25 f26 h23 g24 f25 e26 e25 f23 context memory ssram address. the ssram address outputs identify the ssram locations accessed. cma[18:0] is updated on the rising edge of sysclk.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 38 pin name type pin no. function cmab[17] .. cmab[18] output f24 d26 context memory ssram address bar . these active low address outputs are provided to enable glueless connection to 4 banks of zbt ssram, or 2 banks of late write ssram. in zbt ssram mode, these bits are the inverse of cma[18:17]. in late write ssram mode, cmab[17] is the chip enable bar for even addresses, cmab[18] is the chip enable bar for odd addresses. cmab[18:17] is updated on the rising edge of sysclk. cmrwb output c26 context memory ssram read write bar. cmrwb determines the cycle type when cmceb is asserted low. when cmrwb is asserted high, the cycle type is a read. when cmrwb is asserted low, the cycle type is a write. cmrwb is updated on the rising edge of sysclk. cmceb output d25 context memory ssram chip enable bar. cmceb initiates an access. when cmceb is asserted low, the external ssram samples the address and cmrwb asserted by the s/uni-apex- 1k800. cmceb is updated on the rising edge of sysclk. 9.6 cell buffer sdram interface (52 signals) pin name type pin no. function cbcsb output ae15 cell buffer sdram chip select bar. cbcsb, cbrasb, cbcasb, and cbweb define the command being sent to the sdram. cbcsb is updated on the rising edge of sysclk. cbrasb output af15 cell buffer sdram row address strobe bar. cbcsb, cbrasb, cbcasb, and cbweb define the command being sent to the sdram. cbrasb is updated on the rising edge of sysclk.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 39 pin name type pin no. function cbcasb output ac14 cell buffer sdram column address strobe bar. cbcsb, cbrasb, cbcasb, and cbweb define the command being sent to the sdram. cbcasb is updated on the rising edge of sysclk. cbweb output ad14 cell buffer sdram write enable bar. cbcsb, cbrasb, cbcasb, and cbweb define the command being sent to the sdram. cbweb is updated on the rising edge of sysclk. cba[0] .. cba[11] output ac15 ae16 ad16 ae17 ac16 af18 ad17 ae18 af19 ac17 ad18 ae19 cell buffer sdram address. the cell buffer sdram address outputs identify the row address (cba[11:0]) and column address (cba[7:0]) for the locations accessed. cba[11:0] is updated on the rising edge of sysclk. cbbs[0] .. cbbs[1] output ad15 af16 cell buffer sdram bank select. the bank select signal determines which bank of a dual/quad bank cell buffer sdram chip is active. cbbs[1:0] is generated along with the row address when cbrasb is asserted low. cbbs is updated on the rising edge of sysclk. cbdqm[0] .. cbdqm[1] output ae13 ae14 cell buffer sdram input/output data mask. the data mask changes state from high to low when the sdram is enabled. these pins are held low during normal operation cbdqm is updated on the rising edge of sysclk.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 40 pin name type pin no. function cbdq[0] .. cbdq[31] bidi af3 ae4 ad5 ac6 af4 ae5 ad6 ac7 ae6 ad7 ac8 af6 ae7 ad8 af7 ae8 ad9 ac10 af8 ae9 ad10 af9 ac11 ae10 ad11 ae11 ac12 af11 ad12 ae12 af12 ad13 cell buffer sdram data. the bi-directional cell buffer sdram data bus pins interface directly with the cell buffer sdram data ports. the cell buffer sdram is accessed as a burst of 32-bit long words. cbdq[31:0] is updated/hi-z?d on the rising edge of sysclk. 9.7 microprocessor interface (44 signals) pin name type pin no. function bclk input c1 bus clock. this clock is the bus clock for the microprocessor interface. bclk must cycle at 66 mhz or lower instantaneous rate.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 41 pin name type pin no. function ad[0] .. ad[31] bidi c13 d13 a12 c12 a11 d12 b11 c11 b10 d11 a9 c10 b9 a8 d10 c9 b8 a7 c8 b7 a6 d8 c7 b6 a5 c6 b5 a4 d6 c5 b4 a3 multiplexed address data bus. the multiplexed address data bi-directional bus ad[31:0] is used to connect the s/uni-apex-1k800 to the microprocessor. during the address phase when adsb = 0, ad[1:0] are ignored as all transfers are 32 bits wide. ad[31:0] is sampled/updated/hi-z?d on the rising edge of bclk. adsb input f2 address status. this signal is active-low and indicates a long-word address is present on the address/data bus ad[31:2]. address space used is 0->4k. attempts to access above this address space is prohibited. adsb is sampled on the rising edge of bclk. csb input e1 active low chip select. the chip select (csb) signal is low during the address cycle (as defined by adsb) of s/uni-apex-1k800 register accesses. csb is sampled on the rising edge of bclk.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 42 pin name type pin no. function wr input f3 write/read. the write/read (wr) signal is evaluated when the adsb and csb are sampled active by s/uni-apex-1k800. the buspol input pin controls the polarity of this input. wr is sampled on the rising edge of bclk. burstb input e2 burst bar. this signal is evaluated when the adsb and csb are sample active by s/uni-apex-1k800. when low, this signal indicates that the current access is a burst access (and the blast input can be used to detect the end of the transaction). burstb is sampled on the rising edge of bclk. blast input d1 burst last. this signal indicates the last data access of the transfer. when the burstb input is low, the blast input is driven active during the last transfer of a transaction (even if the transaction is one word in length). when the burstb input is high, the blast input is ignored by s/uni-apex- 1k800. the buspol input pin controls the polarity of this input. blast is sampled on the rising edge of bclk. readyb tri-state f4 ready bar. this signal is asserted low by s/uni- apex-1k800 when the data on the ad[31:0] bus has been accepted (for writes), or when the data on the ad[31:0] is valid (for reads). this signal may be used by s/uni-apex-1k800 to delay a data transaction. this output is hi-z?d one clock cycle after an s/uni-apex-1k800 access, allowing multiple slave device to be tied together in the system. this output should be pulled up externally. readyb is updated on the rising edge of bclk.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 43 pin name type pin no. function btermb tri-state e3 burst terminate bar. this signal is asserted low by s/uni-apex-1k800 when a data transfer has reached the address boundary of a burstable range. attempts to extend the burst transfer after this signal is asserted will be ignored. this output is hi-z?d one clock cycle after an s/uni-apex-1k800 access, allowing multiple slave device to be tied together in the system. this output should be pulled up externally. btermb is updated on the rising edge of bclk. wrdoneb output d2 write done bar. this signal is asserted low by s/uni-apex-1k800 when the most recent write access to internal registers is complete. this signal may be used by external circuitry to delay the issuance of a write operation address cycle until s/uni-apex-1k800 can accept write data. this signal is only needed in systems where the readyb output cannot be used to delay a write data transaction (due to microprocessor restrictions). wrdoneb is updated on the rising edge of bclk. inthib od c4 active low open-drain high priority interrupt. this signal goes low when an s/uni-apex-1k800 high priority interrupt source is active and that source is unmasked. the s/uni-apex-1k800 may be enabled to report many alarms or events via interrupts. inthib becomes high impedance when the interrupt is acknowledged via an appropriate register access. inthib is an asynchronous signal.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 44 pin name type pin no. function intlob od d3 active low open-drain low priority interrupt. this signal goes low when an s/uni-apex-1k800 low priority interrupt source is active and that source is unmasked. the s/uni-apex-1k800 may be enabled to report many alarms or events via interrupts. intlob becomes high impedance when the interrupt is acknowledged via an appropriate register access. intlob is an asynchronous signal. buspol input e4 bus control polarity. this signal indicates the polarity of the wr and blast inputs to s/uni- apex-1k800. when high, the blast pin is active high (high indicates the last word of the burst) and the wr pin is active low (low indicates write). when low, the blast pin is active low (low indicates the last word of the burst) and the wr pin is active high (high indicates write). buspol is sampled on the rising edge of bclk. 9.8 general (10 signals) pin name type pin no. function rstb input aa4 reset bar. this signal provides an asynchronous s/uni-apex-1k800 reset. rstb is a schmitt triggered input with an internal pull-up resistor. oe input ac1 output enable oe is an active high signal, which allows all of the outputs of the device to operate in their functional state. when this signal is low, all outputs of the s/uni-apex-1k800 are hi-z?d, with the exception of tdo . oe has an internal pull up resistor.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 45 pin name type pin no. function sysclk input b12 system clock. this clock is the master clock for the s/uni-apex-1k800 device. all non-any-phy or microprocessor interface related internal synchronous logic is timed to this signal. sysclk must cycle at a 80 mhz or lower instantaneous rate. external ssram and sdram devices share this clock and must have clocks aligned within 0.2ns skew of the clock seen by the s/uni-apex-1k800 device. this clock must be stable prior to deasserting rstb 0->1. nc ab4 ac5 ab23 e23 d22 d5 e24 no connect. these balls are not connected to the die. 9.9 jtag & scan interface (7 signals) pin name type pin no. function tck input ad1 test clock. this signal provides timing for test operations that are carried out using the ieee p1149.1 test access port. tms input ac2 test mode select. this signal controls the test operations that are carried out using the ieee p1149.1 test access port. tms is sampled on the rising edge of tck. tms has an integral pull-up resistor. tdi input ab3 test data input. this signal carries test data into the s/uni-apex-1k800 via the ieee p1149.1 test access port. tdi is sampled on the rising edge of tck. tdi has an integral pull-up resistor.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 46 pin name type pin no. function tdo tri-state ad4 test data output. this signal carries test data out of the s/uni-apex-1k800 via the ieee p1149.1 test access port. tdo is a tri-state output, which is inactive except when scanning of data is in progress. tdo is updated/hi-z?d on the falling edge of tck. trstb input ac3 active low test reset. this signal provides an asynchronous s/uni-apex-1k800 test access port reset via the ieee p1149.1 test access port. trstb is a schmitt triggered input with an integral pull-up resistor. note that when not being used, trstb must be connected to the rstb input. scanen input ad23 scan enable this signal enables the internal scan logic for production testing. should be held to its inactive low state. scanmb input ac22 scan mux this signal is connected directly to the control of the internal scan muxes. should be held to its inactive high state.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 47 9.10 power pin name type pin no. function vdd power ac4 ac9 ac13 ac18 ac23 ad3 ad24 ae2 ae25 b2 b25 c3 c24 d4 d9 d14 d18 d23 j23 j4 n4 p23 v4 v23 the pad ring power pins should be connected to a well de-coupled +3.3 v dc. pch power g4 l4 r4 w4 af5 af10 af17 af22 ab26 u26 k26 g23 d20 a17 a10 d7 the core power pins should be connected to a well- decoupled +2.5 v dc.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 48 pin name type pin no. function vss ground a1 a2 a13 a14 a25 a26 b1 b3 b24 b26 c2 c25 n1 n26 p1 p26 ad2 ad25 ae1 ae24 ae3 ae26 af1 af2 af13 af14 af25 af26 the pad ring and core ground pins should be connected to gnd.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 49 10 functional description this section describes the function of each entity in the s/uni-apex-1k800 block diagram. in this document, receive and transmit are used with the s/uni-apex- 1k800 as the frame of reference. for example, receive is used to describe data paths which are coming into the device. 10.1 any-phy interfaces the s/uni-apex-1k800 interface are any-phy compliant 8/16-bit master/slave interface for both loop and wan ports. the loop and wan interfaces are configured independently. both interfaces are fully compatible with the following any-phy options: ? any-phy master. ? utopia l2 master (ul2m). ? utopia l1 master (ul1m). ? utopia l2 slave (ul2s). 10.1.1 receive interface the s/uni-apex-1k800 requires a 2-byte ingress connection identifier (ici) that uses the 10 lsb (least significant bits). the ici is received with every cell and uniquely identifies the vcc or vpc. the ici can be received within the hec/udf field (16bit i/f only), as a user prepend, or encoded within the vpi/vci field. in any-phy mode, an address prepend is expected to be in the first word/byte of every cell. inclusion of optional words/bytes are statically configured for the interface. the receive cell transfer format is shown in figure 4 and figure 5. figure 4 - 16bit receive cell transfer format bits 15-8 bits 7-0 word 0 (any-phy only) address prepend word 1 (optional) user prepend word 2 h1 h2 word 3 h3 h4 word 4 (optional) hec/udf
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 50 word 5 payload1 payload2 word 6 payload3 payload4 ?? ? ? ? ?? ? ? ? ? ? ? ?? ? ? ? word 28 payload47 payload48 figure 5 - 8-bit receive cell transfer format bits 7-0 byte 0 (any-phy only) address prepend byte 1 (required) user prepend[15:8] byte 2 (required) user prepend[7:0] byte 3 h1 byte 4 h2 byte 5 h3 byte 6 h4 byte 7 (optional) h5 byte 8 payload1 ? ? ? ? ? ? ? ? ? byte 55 payload48 the loop and wan receive master mode interface supports per-device or per- port rpa (receive packet available) status polling via round robin polling address enabling support for up to 32 loop or 4 wan devices and/or ports. polling ceases once a device or port has been identified as having a cell available. polling recommences on the following address that was serviced. since the s/uni-apex-1k800 requires a unique 10-bit ici with every cell,
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 51 knowledge of which polling addresses are associated with devices and which are associated with ports is not required. if ul2m or any-phy, and the number of ports connected is less than 32 (loop) or 4 (wan), there is an option of limiting the polling range; thereby providing optimal polling efficiency. the ul1m is effectively a ul2m without address polling, but retains the port selection handshake. hence a single external ul2s may be connected to the s/uni-apex-1k800 ul1m transmit interface. if any-phy, the s/uni-apex-1k800 expects the any-phy slave device to act as a proxy for its internal ports. the s/uni-apex-1k800 places no restrictions on the number of internal ports within an any-phy slave device. since the polling is tied to the data transfer, both the wan and loop any-phy receive interface is capable of mixing prepend enabled ul2 and any-phy slaves on the same bus with some external glue logic. if ul2s, the s/uni-apex-1k800 operates as a single port utopia l2 transmit slave port. the address pins become inputs and can be configured to respond to any port identifier from 0 to 31 for loop, and 0 to 3 for wan. table 4 - number of ports supported, receive interface mode loop (8/16bit) wan (8/16bit) any-phy master 32 4 utopia l2 master 32 4 utopia l1 master 1 1 utopia l2 slave 1 of 32 1 of 4 10.1.2 transmit interface the transmit cell transfer format is shown in figure 6 and figure 7. word/byte 0 is required for cell transfers to any-phy slaves. the address prepend is the s/uni-apex-1k800 port id associated with the transmit queue in which the cell was en-queued. the unused bits in the address prepend are reserved and devices should not rely on the content. optional word 1 or bytes {1,2} enables the prepending of a 16-bit switch tag. optional word 2 or bytes {3,4} enables the prepending of a 16-bit egress connection identifier (eci). both the switch tag and the egress connection identifier are sourced on a per-vc basis from vc context. the s/uni-apex-1k800 also maps the eci tag to the hec/udf field (word 5) for 16-bit transfer. word 5 or byte 9 is optional. the s/uni-apex-1k800 supports optional vpi and/or vci mapping, selectable on a per vc basis.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 52 inclusion of optional words is statically configurable for the interface. selection of the usage of the included optional words is configurable on a per-vc basis. on a per-vc basis, either mapping of switch tag and/or eci or mapping of the switch tag and vpi, or of vpi and vci is supported. if optional words 2, and/or 5 are included on the interface, they contain the original ici if eci remapping is not supported for the vc. if optional word 1 is included on the interface, it is defined as a reserved field for those vcs that are not mapping the switch tag. figure 6 - 16-bit transmit cell transfer format bits 15-8 bits 7-0 word 0 (any-phy only) address prepend loop i/f: {9 msb reserved, portid[6:0]} wan i/f: {14 msb reserved, portid[1:0]} word 1 (optional) switch tag prepend word 2 (optional) eci prepend word 3 h1 h2 word 4 h3 h4 word 5 (optional) eci prepend word 6 payload1 payload2 word 7 payload3 payload4 ?? ? ? ? ?? ? ? ? ? ? ? ?? ? ? ? word 29 payload47 payload48
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 53 figure 7 - 8-bit transmit cell transfer format bits 7-0 byte 0 (any-phy only) address prepend loop i/f: {msb reserved portid[6:0]} wan i/f: {6 msb reserved, portid[1:0]} byte 1 (optional) switch tag prepend[15:8] byte 2 (optional) switch tag prepend[7:0] byte 3 (optional) eci prepend[15:8] byte 4 (optional) eci prepend[7:0] byte 5 h1 byte 6 h2 byte 7 h3 byte 8 h4 byte 9 (optional) eci prepend[7:0] byte 10 payload1 ? ? ? ? ? ? ? ? ? byte 57 payload48 in the loop interface any-phy mode, 16bit, per-port status polling is supported via a 8-bit polling address bus and a single transmit packet available input enabling up to 128 port polling. 8-bit loop interface is limited to an 8-bit polling address, enabling 128 port polling. the loop interface polling is completely independent of the data transfer. in the wan interface any-phy mode, 8/16bit, per-port status polling is supported via a 3 bit polling address bus and a single transmit packet available input enabling up to 4 port polling. the wan interface polling ceases once a device or port has been identified as having a cell available. wan polling recommences
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 54 on the following address that was serviced. since the polling is tied to the data transfer, the wan transmit interface is capable of mixing prepend enabled ul2 and any-phy slaves on the same bus with some external glue logic. in ul2m, loop interface port selection is done via the 6 lower bits of the 12-bit polling address bus, supporting up to 32 ports. wan interface port selection is done via the 3-bit polling address bus, supporting up to 4 ports. details of the polling algorithm for the loop and wan interface can be found in the loop port scheduler and wan port scheduler section respectively. the ul1m is effectively a ul2m without address polling, but retains the port selection handshake. hence a single external ul2s may be connected to the s/uni-apex-1k800 ul1m transmit interface. specific only to the wan ul1m mode, port address is presented with a programmable value , giving the option of port sparing. in slave mode, the transmit interface operates as a single port utopia l2 receive slave port. the 6 lower bits of the 12-bit loop polling address, or the entire 3 bits of the wan polling address become inputs. the loop interface can be configured to respond to any port identifier from 0 to 31. the wan interface can be configured to respond to any port identifier from 0 to 3. table 5 - number of ports supported, transmit interface mode loop (8 bit) loop (16 bit) wan (8 bit) wan (16bit) any-phy master 128 128 4 4 utopia l2 master 32 32 4 4 utopia l1 master 1 (no sparing) 1 (no sparing) 1 (4 sparing) 1 (4 sparing) utopia l2 slave 1 of 32 1 of 32 1 of 4 1 of 4 10.2 loop port scheduler the s/uni-apex-1k800 loop port scheduler provides weighted interleaved round robin scheduling of up to 128 any-phy addresses. to achieve fairness among the 128 ports and to avoid wasted polling opportunities, the selection of what ports to poll is based on what ports have transmit data queued and have a high probability of being able to accept the cell. the scheduler has 128 polling sequences and 8 different weighting groups. software configures the number of polling sequences a port should participate in
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 55 by assigning a 3-bit logarithmic weight value and a 7-bit sequence number to each port. the scheduler maintains a 7-bit polling sequence number and increments it after each scheduler polling cycle. during a scheduler polling cycle each of the 128 ports is evaluated. the port will be polled if the following conditions are met: ? the port?s transmit data queue is not empty ? the n lsb?s of the scheduler poll sequence number match the n lsb?s of the port?s sequence number (n is equal to the port?s weight). for ports with a weight of zero, this compare is ignored. for ports with a weight of one, then only the lsb is compared. for ports with a weight of seven, then the entire seven bits are compared. to maintain even distribution of ports within the same weight class, software must assign sequence numbers to ports evenly across the 128 polling sequences. this sequence number need only be changed when a port?s weight is changed or the distribution ports in a weight group becomes significantly unbalanced due to port deactivations. sequence numbers and weights may be modified at any time. the logarithmic weights are set so that lower speed ports are evaluated less often relative to higher speed ports. the following formula show relationship between the 3 bit logarithmic weights (lw) and the assigned relative throughput weight (rw) in the case where the aggregate throughput of all the ports is greater than the available bandwidth: rw = 2 (7-lw) the maximum polling rate for any given port is dictated by the number of active ports. in any-phy mode, if only one port is active for all 128 ports (port?s transmit data queue is not empty), the maximum polling rate is governed by the following formula: max. polling rate = f(sysclk) / (64 * 2 lw ) the equivalent equation for ul2m mode is the following: max. polling rate = f(sysclk) / 2 lw 10.3 wan port scheduler the wan port scheduler operates between the queue engine and the multi- channel wan port fifo. the s/uni-apex-1k800 wan port scheduler provides weighted interleaved round robin scheduling of up to 4 wan ports. the dynamic range of the weights is 8 to 1.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 56 the scheduler has 8 polling sequences and 4 different weighting groups. port weighting is achieved by configuring the number of polling sequences a port should participate in. this configuration is done by assigning a 2-bit logarithmic weight value and a 3-bit sequence number to each port. software assigns the 2- bit weight value, and the hardware always maps the 4 ports to the following sequence numbers: port 0 is assigned 000, port 1 is assigned 010, port 2 is assigned 101, and port 3 is assigned 111. the scheduler maintains a 3-bit polling sequence number and increments it after each scheduler polling cycle. during a scheduler polling cycle each of the 4 ports is evaluated. the port will be selected for transmission if the following conditions are met: ? the port?s transmit data queue is not empty ? the n lsb?s of the scheduler poll sequence number match the n lsb?s of the port?s sequence number (n is equal to the port?s weight). for ports with a weight of zero, this compare is ignored and assumed successful. for ports with a weight of one, only the lsb is compared. for ports with a weight of two, only the first two lsbs are compared. for ports with a weight of three, all three bits are compared. ? the s/uni-apex-1k800 internal wan fifo for the port is not full the logarithmic weights are set so that lower speed ports are evaluated less often relative to higher speed ports. the following formula shows relationship between the logarithmic weights values and the resulting linear relative weight. rw = 2 (3-lw) if port 0 were assigned a weight of 0, port 1 a weight of 1, port 2 a weight of 2, and port 3 a weight of 3, and all the ports had data to send, and none of the wan fifos were full, then cells would be transmitted in the following order:
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 57 table 6 - example wirr transmission sequence sequence number ports transmitted 000 0,1 001 0,2 010 0,1 011 0 100 0,1 101 0,2 110 0,1 111 0,3 the above example was constrained by several conditions under which the queue engine wan interface bandwidth was the transmission bottleneck. in the wan transmit datapath, there are actually three places where a transmission bottleneck can occur: the queue engine?s wan interface bandwidth, the any- phy bus, and the actual physical lines. if the queue engine?s wan interface bandwidth is the bottleneck, then the wirr wan scheduler will determine the transmission order. in this case, the queue engine?s wan interface does not have enough bandwidth to service all of the physical lines and each physical line will receive a weighted proportion the queue engine?s available wan bandwidth. if the any-phy bus becomes the bottleneck, then a simple round robin scheduler at the any-phy interface will determine the transmission order. for this reason, the system designers should ensure that the any-phy bus does not become the bottleneck. finally, if the physical lines are the bottleneck, then the physical line rates and the wirr wan scheduler will determine the transmission order. this last situation is the most desirable one because in this case no transmission opportunities will ever be missed. 10.4 wan port aliasing for each of the four channels, a port aliasing register is provided to allow for port sparing for the uplinks. these registers map the internal vc?s portid to the external any-phy address. by having this layer of indirection, it is possible to re- direct all traffic from one any-phy address to another by modifying a single register, and without having to change any per-vc context information.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 58 10.5 wan and loop ici selection the s/uni-apex-1k800 requires that an ici be received with every cell. a connection identified by a single ici may be either a vcc or a vpc connection. the ici may be prepended to the cell or embedded in the vpi/vci header for interfacing to devices that cannot add prepends to the cell. the s/uni-apex-1k800 accepts cells from the following sources: wan ports, loop ports, and the microprocessor port. each cell is directed to a particular connection, which is identified by an ici. for cells from the microprocessor port, the ici is given directly. for the wan and loop ports, this ici may be selected from one of several locations within the cell and is programmable per interface (of the 2 byte prepend only 10 lsb are used): ? a two byte user tag prepended to the cell. ? the two byte hec/udf field of the cell. ? embedded in the 12 bit vpi & 16 bit vci field as defined as follows: if the vpi < ?fff? then ici = ?0? & vpi; -- this connection is a vpc connection., -- vpi cannot be set to a value larger than "3ff" else ici = "0" & vci; -- this connection is a vcc connection. -- vci cannot be set to a value larger than "3ff" end if; in an uni environment, the s/uni-apex-1k800 considers the 4 bit gfc field plus the 8 bit vpi field as the vpi field described above. 10.6 microprocessor interface the microprocessor interface supports the following features: ? 32-bit wide multiplexed address data bus. ? synchronous microprocessor interface supporting linear bursts of up to 16- long words for cell transfers, up to 5 long words for performance sensitive
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 59 context memory, and single long word accesses for registers and remaining context memory. ? microprocessor clock independent of the system clock, allowing for easy integration into any host system without altering device performance. ? addressing: ? direct addressing for internal control and status, sar assist, cbi register port and memory port. ? indirect addressing (via the memory port) for context memory accesses. ? indirect addressing (via the cbi register port) for cbi register accesses. ? high and low priority interrupt outputs provided for efficient task management. ? bus polarity select pin provided to allow interconnect between the s/uni- apex-1k800 and powerpc or i960 microprocessors. ? write done indicator output provided to allow interconnect with the idt mips microprocessor (with minimal external logic for system command generation and interpretation). the microprocessor interface receives a multiplexed address and data bus, where an address strobe input defines the address cycle. during the address cycle, the bus contains the address for the beginning of the transaction. also during this cycle, the chip select, write indicator, and burst indicator are latched to define the transaction. the interpreted polarity of the write indicator and burst indicator are controlled by a single configuration input pin, for compatibility with multiple microprocessors such as the powerpc or the i960. if a read transaction is indicated at the address cycle, then s/uni-apex-1k800 will respond with a ready indicator concurrent with each long word of valid data, until the burst is complete. the delay between the address cycle and the first valid long word of read data is variable, depending on the specific register address (not less than 2 clock cycles). if a read transaction is issued to the receive sar when no data is available, or issued to the memory port when the current command is not yet complete, the first word of valid read data will be delayed until data is available (this can be many clock cycles). if excessive delay for the first word of valid read data cannot be tolerated, then polling (or interrupt processing) must be used for accesses to these regions. the ready indicator may be deasserted by s/uni-apex-1k800 in the middle of a burst read operation to allow for read data synchronization delay.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 60 if a write transaction is indicated at the address cycle, then s/uni-apex-1k800 will respond with a ready indicator concurrent with each long word of valid data, until the burst is complete. the delay between the address cycle and the first valid long word of write data is variable, depending on the specific register address (not less than 1 clock cycle). if a write transaction is issued to the transmit sar when the buffer is full, or issued to the memory port when the current command is not yet complete, the first word of valid write data will be delayed by the ready indicator until buffer space is available (this can be many clock cycles). if excessive delay for the first word of valid write data cannot be tolerated, then polling (or interrupt processing) must be used for accesses to these regions. once the ready indicator has been asserted, it will remain asserted until the completion of the burst. an additional output is provided to indicate when the current write operation is complete (write done indicator). processors which do not allow the ready indicator to be used to delay the advance of write data, but do allow a write operation to be delayed before it is issued (such as the idt mips processor) may use this output. the write done indicator is asserted when s/uni-apex- 1k800 can accept another write command. typically, an external circuit may be employed which uses this s/uni-apex-1k800 output to determine when to allow the processor to issue another write command. when this output is used prior to the address cycle, the normal ready indicator need not be used for write operations, as s/uni-apex-1k800 can accept write data always once the write done indicator is asserted (unless polling of buffer status is disabled). note that polling of buffer status must be employed when the processor does not allow the ready indicator to be used to delay the advance of write data. if a burst is indicated at the address cycle, then the transaction will not complete until the processor asserts the burst last indicator. if a burst is not indicated, then the transaction will be completed after the ready indicator is asserted by s/uni- apex-1k800. the multiplexed address/data bus will be hi-z?d immediately following the last word of read data to allow a new address cycle to commence. the microprocessor interface will allow an address cycle to occur with no wait states between the last word of valid data and the new address; however, care must be taken to minimize bus contention in the system design if no wait states are provided by the microprocessor. the diagrams below illustrate possible connections between the s/uni-apex- 1k800 and various microprocessors. for the i960 interface, the two lower order bits of the address may be tied to ground as all accesses to the s/uni-apex- 1k800 are 32bits wide.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 61 figure 8 - i960 (80960cf) interface bclk ad[31:0] adsb csb wr burstb blastb readyb btermb wrdoneb buspol pclk[2:1] a[31:2] be#[3:0] d[31:0] ads# w/r# blast# ready# bterm# boff# hold holda i960 (80960cf) vcc figure 9 - powerpc (mpc860) interface bclk ad[31:0] adsb csb wr burstb blast(b) readyb btermb wrdoneb buspol clkout a[31:0] dp[3:0] d[31:0] ts# r/w# burst# bdip# ta# bi# tea# br# bg# mpc860 vcc
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 62 10.7 memory port much of the configuration information that s/uni-apex-1k800 requires for normal operation is accessed indirectly through the memory port, as the configuration storage is tightly coupled to performance. register arrays are provided to allow access to the following memory apertures: ? external queue context ? internal queue context ? internal loop context the memory port is primarily used for context setup, but may also be used for diagnostic purposes. features include ? control register allows the microprocessor to specify the aperture, address, and length of the burst. access to the internal loop context are restricted to single long word accesses. ? 4-word burst write buffer with 8-bit overflow register, supporting writes of up to 4 contiguous 34-bit words to valid apertures. ? masked write mechanism, which can be used to overwrite specific bits of 1 word without affecting other bits. ? 4-word burst read buffer with 8-bit overflow register, supporting reads of up to 4 contiguous 34-bit words from valid apertures. ? memory port status provided in the low priority interrupt status register, allowing for polling or for interrupt driven accesses to memory. memory is accessed using a 4-long word address in the control register, along with 4 long-word enables. this approach allows non-contiguous bursts within a 4-long word section of memory, or to specify which long word is to be accessed in single long word transfer. (for example, the first and third word of a section may be modified without changing the second and fourth). to compensate for the difference between the 34-bit context memory bus and the 32-bit microprocessor bus, an 8-bit overflow register is provided for both reads and writes. the overflow register represents the most significant 2 bits of up to 4 words in a burst access. in this manner, 4 34-bit words can be accessed using a 5-word burst on the microprocessor bus.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 63 the masked write mechanism is provided to allow the microprocessor to change a field within a word in context memory while traffic is present, without risk of context corruption. the masked write can be performed on one word per operation. in this mode (as indicated in the control register), the second word in the 4-word burst write buffer and the second pair of bits in the overflow register represent a bit mask which will be used by s/uni-apex-1k800 to perform a masked write function. 10.8 sar assist the sar assist module allows cells or aal5 frames to be transferred to and from the queue engine. burst transfers from the microprocessor into and out of the sar staging buffers enable efficient access to the queuing structures. the staging buffers are organized as 64 byte units, including the ici/eci, the cell header, the payload, and control or status information. a complete buffer can be written or read in one continuous burst, or the data can be accessed individually or with a series of shorter bursts. within this structure, both the cell header and the payload are aligned on 32-bit boundaries, to simplify microprocessor access. the sar assist module can also optionally perform calculation, checking, and insertion of aal5 crc32 or crc10. one staging buffer is provided for cell or frame injection, while four staging buffers are provided for cell or frame reception (one for each microprocessor class queue). 10.8.1 transmit the transmit function of the sar has the following features: ? read staging buffer for each of the 4 class queues associated with the microprocessor. ? crc-32 checking for aal5 re-assembly. ? simultaneous re-assembly assist on all 4 class queues. ? crc-10 checking for oam. ? cell header is provided with each pdu, including pti for end-of-message detection by the microprocessor. each read buffer represents a 2-cell pipeline, providing minimum latency for cell retrieval. while a cell is read out, a second cell is retrieved from the queue engine automatically. by having read buffers for each class, the microprocessor can decide which class has the highest priority. the microprocessor can
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 64 interrupt the retrieval of a frame from one class to transmit a higher priority packet/cell from another class without impacting the crc32 calculation. the sar will accept another cell from the queue engine when the 14 th long word of the transmit buffer has been read. the sar assist transmit cell transfer format is shown in figure 10. figure 10 - sar assist transmit cell transfer format register bits 31-24 bits 23-16 bits 15-8 bits 7-0 sartxdata0 crc status sartxeci sartxdata1 h0 h1 h2 h3 sartxdata2 payload1 payload2 payload3 payload4 ? ? ? ?? ? ? ?? ? ? ?? ? ? ? ? ? ? ?? ? ? ?? ? ? ?? ? ? ? ? ? ? ?? ? ? ?? ? ? ?? ? ? ? sartxdata13 payload45 payload46 payload47 payload 48 the sar performs crc32 error checking over the entire frame. the crc32 accumulator for a class is automatically reset on frame boundaries or when a non-user or wfq cell is encountered (see table 8). a crc32 status bit is updated as the eom cell enters the read buffer. the sar performs crc10 error checking over an oam cell. a crc10 status bit is updated as the oam cell enters the read buffer. the processor should verify the cell type (via the cell header) when determining the validity of these status bits. all the crc status bits in the buffer are updated prior to indicating data is available. should a crc error be detected, the microprocessor can skip reading the cell?s entire payload and move on to the next cell by reading the 14 th word of the transmit buffer. 10.8.2 receive the receive function of the sar has the following features: ? single write staging buffer ? ici (ingress connection identifier) prepended to all cells ? option to overwrite the end of a cell with aal5 crc32 or oam crc-10
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 65 the single write buffer represents a 2-cell pipeline, allowing the microprocessor to fill one payload while the other one is waiting to be queued. a not full status bit is provided, indicating whether the write buffer is capable of accepting at least one cell. cell enqueuing is initiated by writing to the 14 th word of the receive buffer. the sar assist receive cell transfer format is shown in figure 11. figure 11 - sar assist receive cell transfer format register bits 31-24 bits 23-16 bits 15-8 bits 7-0 sarrxlword0 crc control sarrxici sarrxlword1 h0 h1 h2 h3 sarrxlword2 payload1 payload2 payload3 payload4 ? ? ? ?? ? ? ?? ? ? ?? ? ? ? ? ? ? ?? ? ? ?? ? ? ?? ? ? ? ? ? ? ?? ? ? ?? ? ? ?? ? ? ? sarrxlword13 payload45 payload46 payload47 payload 48 once there are 2 cells in the process of being en-queued, any further attempts to write to the write buffer will be held pending until the first cell has been en- queued. the crc control gives each cell the option of being overwritten with an aal5 crc-32 or an oam crc-10 trailer. these crc values cannot be invoked if oam cells are interspersed within aal5 packets. for frame traffic, it is necessary to write sarrxlword0&1 for the first two cells, sarrxlword0 for the third cell and sarrxlword0 for the last cell of the frame sarrxlword0&1 write of the first cell is required to reset the crc, and establish the ici and header for the first pipe. sarrxlword0&1 write of the second cell is required to set the crc for normal operation, and establish the ici and header for the second pipe. sarrxlword0 write of the third cell is required to remove the reset of the crc established in the first cell and set the crc for normal operation. sarrxlword0 write of the last cell is required to concatenate the crc onto the end of the cell. the middle cells of the frame only require the payload to be updated. 10.9 queue engine the queue engine performs the following functions:
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 66 ? service arbitration ? congestion control ? statistics ? cell queuing (vc scheduling) ? class scheduling ? watch dog: vc time out patrol and re-allocation ? microprocessor queue buffer re-allocation 10.9.1 service arbitration there are 9 components that request services from the queue engine. three components (sar rx, wan rx, and loop rx) can request a cell to be en- queued. another three components (sar tx, wan tx, and loop tx) can request a cell to be de-queued. the shaper, if enabled, can request the transmission slots to be advanced (see section on shape fair queuing). there are two possible requests from the watch dog, one to patrol a range of vc queues to detect a timed out vc, and another request to re-allocate buffers from a vc that has timed out. the up can request a vc or class queue to have their buffers re-allocated and removed from service. the queue engine is capable of simultaneously servicing any one or all of the requests from an en-queue component, a de-queue component, watch dog patrol and transmission slot advancement. the queue engine is capable of servicing the re-allocation of buffers from either the up or watch dog alone. to resolve all these requests, there are four arbitration units. see figure 12.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 67 figure 12 - service arbitration hierarchy rx arbiter tx arbiter rr arbiter up re-allocate watch dog re-allocate sar rx i/f wan rx i/f loop rx i/f sar tx i/f wan tx i/f loop tx i/f ?queue arbiter? queue engine watch dog patrol advance txslot rr arbiter there is a rx arbiter that receives requests to queue a cell from the sar, loop and wan rx interfaces. there is a tx arbiter that receives requests to de-queue a cell from the sar, loop and wan tx interfaces. these rx and tx arbiters have two options for arbitration. the default option is to have the arbiters use round robin to select between the three interfaces. the alternate option is to have the arbiters use round robin between the loop and the wan interfaces, with the sar set to the lowest priority. the results of the rx and tx arbiters, along with the request from the watch dog patrol and the shaper transmission slot advancement, are or?d together to represent a single request from the ?queue arbiter?. there is a round robin arbiter that receives re-allocation requests from the watch dog and up. the results of this arbiter, and the one from the ?queue arbiter? goes to the final round robin arbiter. 10.9.2 cell queuing after congestion control, a cell will be queued onto a linked list structure. the structure is made up of context records, on a per-port, per-class, and per-vc basis. context records are stored in both the external ssram and internal ram. figure 13 below illustrates the structure of the linked lists, and the relationships between the different context records.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 68 figure 13 - queue linked list structure port record group max. 128 for loop max. 4 for wan max 1 for up cell record 64-256k vcrecord group max. 1024 cell flow class0 class1 class2 class3 class queue vc queue note: the class queue and vc queue as illustrated in the above diagram cannot be directly correlated with the per-class and per-vc levels as defined in the congestion control. the rules for queuing, and the way the linked lists are utilized is configured on a per-vc basis. a vc may be configured to one of three mutually exclusive queuing procedures. in addition, the queuing of non user cells may be handled differently. the available queuing procedures as a function of the port destination are outlined in table 7.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 69 table 7 - available queuing procedures loop wan up weighted fair queuing xxx frame continuous queuing x x x shape fair queuing x non user cell queuing x x x 10.9.2.1 weighted fair queuing weighted fair queuing is available to cells destined for the loop, up and wan ports. it is configured on a per-class basis. the vc and class queue work together to provide weighted fair queuing. the class queue is a staging area for cells from different vcs to be lined up for their final destination. the vc demographics in the class queue are defined by each vc?s scheduled weight. the wfq maintains n cells from a vc in the class queue, where n is the weight of the vc. if greater than n cells exist, the excess is maintained in the vc queue. cells are transferred from the vc queue to the class queue to maintain the vc weight in the class queue. 10.9.2.2 frame continuous queuing frame continuous queuing, or vc merge is available to all ports. it is configured on a per-vc basis. the vc queue is transformed into a frame re-assembly area. frame traffic is assumed to use the aal5 eom pti field indicator to delineate frame boundaries. frames are completely assembled in the vc queue before being transferred over to the class queue. non-user cells encountered on fcq vcs are handled differently. please refer the section on non-user cell queuing. the maximum length of the re-assembled frame can be one of two globally defined sizes, selected on a per-vc basis. should a vc that is in process of re- assembly exceed the maximum length, a frame discard will be invoked. the cells in the vc queue will be discarded, as well as the cells that are about to be received up to and including the eom. from a statistical count perspective, this frame discard is identical to a frame discard caused by congestion. in addition, a per-vc maskable interrupt is invoked and the ici is stored in a register that only holds the ici of the last vc that violated the maximum re-assembly length. if a frame has a zero length field in the aal5 trailer, there is a per-vc context parameter vclenchken that will configure the queue engine to perform an frame discard. as with the maximum length frame discard, this zero length frame
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 70 discard is identical to a frame discard caused by congestion from a statistical count perspective. a vc timeout watchdog is provided to protect memory resource should a re- assembly not complete in a timely manner. there are two procedures that are carried out by the watch dog. the first procedure is the patrol, which is performed by the queue engine during regular cell en-queue and de-queue sequence. within the context record, there is a re-assembly parking state bit, reaspark. the watch dog has a current re-assembly parking state bit, currentreaspark. whenever a user cell (ie not rrm or oam cell) arrives, the reaspark state bit is set to the currentreaspark. the watch dog, initiated by the microprocessor, will walk through a programmable range of marked vcs, that are currently being re-assembled, to check and see if reaspark = currentreaspark. if this is true, then the vc is deemed ok. if it finds a valid vc with reaspark != currentreaspark, the vc is deemed dead. the discovery of a dead vc initiates the watch dog re-allocation procedure. when the patrol is complete, the currentreaspark bit is automatically inverted to prepare for the next patrol. the watch dog re-allocation procedure is performed between the cell receive/transmit servicing. all the buffers in the vc queue are reclaimed, the vc q congestion counters are reset to zero, the general discard count is updated, and vc status is reset to receive the next incoming cell as a bom. a per-vc maskable interrupt is invoked and the ici is stored in a register that only holds the ici of the last timed out vc. 10.9.2.3 shape fair queuing the s/uni-apex-1k800 shaper is a passive dual rate shaper based on a time slot design. it will shape on a per vc basis, to the traffic parameters pcr, scr & mbs. traffic shaping is available on the four wan ports, but not on the loop ports. a maximum of four out of the sixteen wan port classes (four ports, four classes per port) can have shaping applied to their output. every vc connected to a shaped class will have shaping applied to it, but each vc can have a unique shape rate. classes that are not shaped can coexist on the same port as classes that are shaped, and there can be more than one shaped class on a single port. each shaper has a fundamental time unit, qshpnrtrate, which defines the minimum time increment between successively scheduled cells. although each shaper is independent, the aggregate shape rate (1/qshpnrtrate) of the active shapers must be less than the device overall cell rate limit (1.42mc/s @ 80mhz). the vc?s scr is defined by the number of fundamental time units, shpincr, inserted between the vc?s cell as they are scheduled by the shaper. the scr is
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 71 proportional to 1/shpincr. the cdv introduced is within 1 fundamental time unit. when there is neither contention (brief period where multiple vcs are scheduled to transmit at the same time) nor congestion (over-subscription of the port/class), the shaper will always transmit at scr. see ideal emission of figure 14. the pcr and mbs only come into effect when the vc experiences one or more periods of contention or congestion (and hence the term passive dual rate shaper). an internal ?late counter? is maintained that represents how late the current cell?s scheduled emission time slot is relative to the ideal emission time slot. a non-zero late counter will cause the shaper to attempt to recover the lost opportunities by scheduling the cell with an increment value no smaller than shpincr ? shpcdvt. the shpcdvt parameter, user defined on a per-vc basis, is in terms of the shaper?s fundamental time unit. the difference (shpincr ? shpcdvt) is minimum number of fundamental time units inserted between cells, and is proportional to the vc?s 1/pcr. given the opportunity, the shaper will burst at pcr rates until the late counter returns to zero 1 . the size of the counter, programmable on a per-vc basis, therefore defines the mbs. see case #1 of figure 14. if congestion persists for an extended period, the late counter will continue to accumulate and eventually wrap around once mbs is reached. the resulting emission pattern is one where the duration of bursting is the remainder of the rolled counter. every time the counter wraps, a cdv, equal to the mbs, is introduced into the emission stream. recovery of the cumulative cdvs can only occur if the ingress stream pauses long enough for the vc queue to empty entirely. maxcdv can be imposed by limiting the length of the vc queue via the per-vc max congestion threshold. see case #2 of figure 14. 1 note that the inter-cell transmission times may actually exceed 1/pcr. factors include the number of active wan ports, the number of active loop ports, and back pressure created by the external wan port.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 72 figure 14 - traffic shaping on the wan port time ideal emission 1234567 1 2 3456 7 1235 case #1 emission after contention, within burst limit case #2 emission after contention, beyond burst limit 8 8 6 4 0 0 0 1/scr 1/pcr <= mbs cdv for vcs that are shaped to rates approaching the fundamental time unit, there is the issue of granularity caused by the nature of time slots. for example, if the fundamental time unit is the equivalent of 100mb/s, the maximum shaped rate is 100mb/s (shpincr = 1), the next possible shaped rate is 50mb/s (shpincr = 2). in order to achieve shaped rates between 100mb/s and 50mb/s, the shpincr may be defined as an integer plus a fractional component. the shaper will schedule a cell to its integer value of shpincr, while maintaining a remainder count of the fractional portion. whenever the remainder count exceeds a unit value, the shaper will schedule the next cell to the integer value + 1. the effective scr rate over time will be the correct rate, but a cdv equal to the fractional value is introduced into the egress stream. if the shpincr is an integer value, then there is no additional cdv introduced due to time slot granularity. pcr and mbs parameters are not supported when non-integer shpincr is invoked. see figure 15 where the shpincr has been set to 1.5.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 73 figure 15 - non-integer shpincr emission with shpincr = 1.5 fundamental time slots user programming can also define the action of the shaper when overall egress congestion (i.e. too much traffic being sent through the shaper) is causing all vcs on that port/class to experience shaping delay due to congestion. when congestion is detected, the shaper will temporarily increase the fundamental shaping time unit, thereby causing each vc to schedule cells less frequently. this will eventually relieve the congestion, at which point the time unit will be brought back to its previous value. the impact of the congestion is distributed fairly across all vcs on the congested port because all vcs on the port experience the same relative decrease in scheduling frequency. 10.9.2.4 non-user cell queuing when a non-user cell is encountered, it may be queued with special handling. the cases requiring special handling are: ? cells identified as an end to end oam may be redirected to the up?s class 0 queue. this can occur independent of the queuing mechanism selected for the vc (wfq, fcq, and sfq). ? cells identified as a segment oam may be redirected to the up?s class 0 queue. this can occur independent of the queuing mechanism selected for the vc (wfq, fcq, and sfq). ? during fcq, a cell identified as an oam that is not being redirected to the up will bypass the vc queue re-assembly area and go directly to the class queue. ? during fcq, a cell identified as an rrm (reserved or resource management) will bypass the vc queue re-assembly area and go directly to the class queue. the table below lists the rules used to identify oam and rrm cell types.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 74 table 8 - oam & rrm cell identification type parameter location vcvpc = 1 vc context vpc end to end oam vci = 4 cell header vcvpc = 1 vc context vpc segment oam vci = 3 cell header vcvpc = 0 vc context vcc end to end oam pti = 5 cell header vcvpc = 0 vc context vcc segment oam pti = 4 cell header vcvpc = 0 vc context rrm pti = 11x cell header vpc/vcc end to end oam cells will be redirected to the up?s class 0 queue if the context parameter vceeoam = 1, independent of the queue method selected. if vceeoam = 0 and fcq is selected, then the cell will be queued directly onto the class queue. vpc/vcc segment oam cells will be redirected to the up?s class 0 queue if the context parameter vcsegoam = 1, independent of the queue method selected. if vcsegoam = 0 and fcq is selected, then the cell will be queued directly onto the class queue. non user cells not meeting any of the above conditions will not be redirected and will be treated like a normal user cell in terms of queuing. the re-direction applied on oam cells will preclude any performance measuring sessions on vcs that are programmed with fcq. 10.9.3 class scheduling class scheduling is performed on the loop and wan ports. there is no class scheduling for the up ports as all four classes are accessible simultaneously. the class scheduler provides modified priority scheduling with class zero having the highest priority and class three having the lowest. the high priority classes can be utilized for real time services such as cbr and vbr-rt. the lower priority classes can be utilized for vbr-nrt, gfr and ubr services. there are three configurations for class scheduling:
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 75 ? strict priority, round robin or modified strict priority between classes, evaluated after the transmission of each cell. ? strict priority between classes, evaluated after the transmission of an entire packet, and available only to those vcs configured for fcq. ? strict priority between classes, evaluated after the transmission of a partial packet of a programmable length, and available only to those vcs configured for fcq. 10.9.3.1 cell and packet scheduling in order to ensure that the lower priority classes are not starved when the high priority classes are under heavy utilization, a minimum bandwidth reservation scheme is employed. the user can program the minimum bandwidth requirements of classes one, two, and three and thus avoid starvation. setting the minimum bandwidth requirements to zero (classxcelllmt = 0) on all classes will result in the class scheduler acting as a strict priority scheduler. setting the minimum bandwidth requirements to three (classxcelllmt = 3) on all classes will result in the class scheduler acting as a round robin scheduler. the mechanism utilized to ensure that a class does not starve is as follows. the class scheduler keeps track of the number of missed transmit opportunities the lower priority classes within a port have had. when a cell is transmitted on a particular class the classxcellcnt counters are incremented for all other classes which have missed an opportunity to transmit a cell. once the classxcellcnt for a class reaches a maximum value (as defined by classxcelllmt), the class is in starvation. on the next cell transmit opportunity for that port, the starving class will be allowed to transmit one cell. if multiple classes were indicating starvation then the highest priority class would transmit first, then the next class until all starving classes have been serviced. a starving class is only allowed to transmit one cell at a time. this ensures that the higher priority classes do not experience a large amount of cdv caused by the lower priority classes. when a class has an opportunity to transmit (due to starvation avoidance or otherwise), its classxcellcnt is reset and the above procedure is repeated. a per-port parameter, classpacket, is provided to support continuous packet transmission. in this packet mode, a vc that is configured for fcq will retain permission to transmit cells for the length of the entire packet, regardless of the starvation states of the other classes, including class 0. this feature enables traffic to be emitted from the s/uni-apex-1k800 packet contiguously and thus minimizing the buffering requirements for an external sar device. strict priority must be set whenever packet class scheduling is selected.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 76 it is possible to mix vcs that have fcq and wfq scheduling within the same class, and classpacket enabled. non fcq vcs and non-user cells (as defined in table 8) are treated as single cell packets. all counters, control and limit fields for the class scheduler are located in the class scheduler context memory. as stated earlier, memory is only allocated for classes one, two, and three. class zero does not require any class scheduler context information. 10.9.3.2 partial packet scheduling a per-port parameter, classfragen, is provided to support packet fragmentation. in this fragmentation mode, classes are selected on a strict priority basis. once a class is selected, the packet at the head of the class queue is transmitted up to a programmable length or until the eom is encountered, whichever comes first. non fcq vcs and non-user cells (as defined in table 8) are treated as single cell packets. when the length/eom is reached, the classes are evaluated once again in a strict priority. the transmission of the original packet will resume once the original class regains transmission rights. note that by virtue of the strict priority scheduling, class0 will always have its packets transmitted in their entirety. 10.9.4 congestion control the congestion control decides whether to permit a cell to enter the queue structure. the objective is to provide a minimum reserved buffer allocation to all active vcs and to fairly allocate shared buffer resources to eligible vcs. the algorithm is applied to both frame and non-frame traffic. the objectives of the algorithm are as follows: ? provide guaranteed resources to all active vcs ? share available buffer resources to eligible vcs with excess buffering requirements ? restrict resource allocation on a per-vc, per-class, per-port, and per- direction basis to those levels that have exceeded their allotment of resources. ? avoid global synchronization ? provide interrupts and id of the last maximum threshold discard invoked. these objectives are achieved by having several thresholds and hierarchical count values, at the per-device, per-direction, per-port, per-class, and per-vc
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 77 levels. figure 16 illustrates the relationship between the hierarchical count values and their associated thresholds. figure 16 - thresholds and count definitions classcnt classclp1thrsh classclp0thrsh classmaxthrsh max. 256k - 1 cells portmaxthrsh max. 256k - 1 cells per-class (4 per port) portcnt per-port (128 loop, 4 wan, 1 up ) vcclp1thrsh per-vc(clp0) vcclp0cnt vcclp0minthrsh portclp1thrsh portclp0thrsh dirmaxthrsh max. 256k -1 cells dircnt per-direction (1 loop, 1 wan) dirclp1thrsh dirclp0thrsh per-vc (aggregate max. 1k vc) vcmaxthrsh max. 8k-1 cells vccnt = vcqclp01cnt + vcclassqclp01cnt vcclp0thrsh initial state of freecnt max. 256k - 1 cells freecnt per-device each hierarchical level has three population zones, each with its own discard rules: 1) plenty of resources available, no discard 2) some resources available, discard all cells with inbound clp state = 1 3) restricted resources available, discard all cells except cells that have inbound clp state = 0 and have not met their minimum allocation of resources (vcclp0minthrsh).
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 78 no equivalent per-direction count and threshold for up destined cells, since there is only 1 up port. all counts represent the number of cells found at the hierarchical level, with the exception of freecnt at the per-device level. the freecnt count value represents the number of free buffers remaining in the device. the initial value of freecnt is defined by the user. the congestion algorithm has three possible definitions for clp: 1) cell clp, the clp found in each cell?s header; 2) bom clp, the clp found in the frame bom cell?s header; 3) or clp, the running or of all received user cell?s clps since the bom of a frame. non-user cells do not affect the state of the running or clp. depending on the vc configuration, anyone of these three definitions can be used to increment a congestion count, or to select a threshold when comparing to a count. when the queue engine receives a cell, the congestion control will apply the discard rules at each hierarchical level. only when a cell has passed through each hierarchical level without being discarded will it be permitted entry into the queue. setting the max threshold to zero on any given hierarchical level will effectively disable congestion discards at that hierarchical level. exception to this rule is the vcmaxthrsh, which will always have the 8k-1 limit. the xxxclp0thrsh thresholds must always be set greater than or equal to the xxxclp1thrsh thresholds. there are several error flags set whenever a non-zero maximum threshold is exceeded. table 9 correlates the interrupts and context record identification parameters to the corresponding maximum threshold. table 9 - congestion error flags threshold interrupt identification vcmaxthrsh qvcmaxthrsherr (maskable on per-vc basis) vcmaxthrsherrid classmaxthrsh qclassmaxthrsherr classmaxthrsherrid classmaxthrsherrportid portmaxthrsh qportmaxthrsherr portmaxthrsherrid
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 79 dirmaxthrsh qdirmaxthrsherr check wancnt or loopcnt freecnt = 0 qfreecntzeroerr n/a efci marking may be performed on cells as they are transmitted out of the queue, based on the state of congestion at the time of transmission. marking of efci is per vc selectable to occur at either the clp1 thresholds or the clp0 thresholds. a cell will be marked if hierarchical count values exceed one of the clp1 thresholds (vcclp1thrsh, classclp1thrsh, portclp1thrsh, dirclp1thrsh) or one of the clp0 thresholds (vcclp0thrsh, classclp0thrsh, portclp0thrsh, dirclp0thrsh), and the third bit of the pti field in the cell is zero (pti = 0xx). there are three unique congestion discard rules. the selection of the rule to be applied is based on the cell type (user or non-user), the queuing mechanism, and finally the congestion type. if it is a non-user cell, the congestion mode is always cell discard. if shaping is not enabled for the destination port/class, the discard rule is selected on a per-vc basis, and is a function of the queue mechanism selected (vcqueue), as well as a per-vc congestion context parameter (vccongmode). if the port/class is shaped, only two of the three rules is available, and is selectable on a per-vc basis. table 10 below illustrates how the congestion discard rule is selected. table 10 - congestion discard rules selection cell shaped vcqueue vccongmode congestion mode user no 0 (wfq) 0 epd/ppd discard user no 0 (wfq) 1 cell discard user no 1 (fcq) x fcq discard user yes x 0 epd/ppd discard user yes x 1 cell discard non-user x x x cell discard oam cells that are redirected to the microprocessor are subject to cell discard rules applied to the up congestion counts at the per-port and per-class levels. there is no congestion control at the vc level for these redirected oam cells.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 80 10.9.4.1 epd/ppd discard figure 17 - epd/ppd congestion discard rules classclp1thrsh classclp0thrsh classmaxthrsh portmaxthrsh per-class per-port vcclp1thrsh portclp1thrsh portclp0thrsh dirmaxthrsh per-direction dirclp1thrsh dirclp0thrsh per-vc vcmaxthrsh vcclp0thrsh invoke epd on bom invoke ppd on com/eom when portcnt >= portmaxthrsh invoke epd on bom invoke ppd on com/eom when classcnt >= classmaxthrsh invoke epd on bom invoke ppd on com/eom when vccnt >= vcmaxthrsh no discard invoke epd on clp1 frame when xxcnt >= xxclp1thrsh invoke epd on clp0, clp1 frame when xxcnt >= xxclp0thrsh except clp0 frame having vcclp0cnt < vcclp0minthrsh invoke epd on bom invoke ppd on com/eom when dircnt >= dirmaxthrsh when freecnt = 0 invoke epd on bom invoke ppd on com/eom initial state of freecnt per-device invoke epd on clp0, clp1 frame when vccnt >= vcclp0thrsh when epd/ppd discard is selected, the discard mechanism uses the aal5 eom pti field indicator to delineate frame boundaries epd discard is evaluated only when the bom is received, and is based on the bom clp state. the vcclp0cnt increments when a received cell passes congestion and the inbound clp state is zero. the vcclp0cnt decrements when the outbound clp state is zero. the in/outbound clp state is defined by the per-vc context parameter, vcgfrmode. when vcgfrmode = 0, the in/outbound clp is
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 81 defined by the receiving/transmitting cell clp state, respectively. when vcgfrmode = 1, the in/outbound clp is defined by the receiving/transmitting frame?s bom clp state, respectively. if a ppd discard is invoked, the eom will not be discarded unless one or more of the hierarchical count values is greater than or equal to the dir/port/class/vc maxthrsh at the time the eom is received. if the eom is discarded, the following frames will be discarded and the congestion status will remain in ppd until an eom is accepted. in the case when vcgfrmode = 1, the bom clp state of the first frame will be used to define the clp state of the following discarded frames. 10.9.4.2 cell discard figure 18 - cell congestion discard rules classclp1thrsh classclp0thrsh classmaxthrsh portmaxthrsh per-class per-port vcclp1thrsh portclp1thrsh portclp0thrsh dirmaxthrsh per-direction dirclp1thrsh dirclp0thrsh per-vc vcclp0thrsh discard cell when freecnt = 0 discard cell when portcnt >= portmaxthrsh discard cell when classcnt >= classmaxthrsh no discard initial state of freecnt per-device discard cell when dircnt >= dirmaxthrsh discard cell when vccnt >= vcclp0thrsh discard clp1 cell when xxcnt >= xxclp1thrsh discard clp0, clp1 cell when xxcnt >= xxclp0thrsh except clp0 frame having vcclp0cnt < vcclp0minthrsh
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 82 when in cell discard mode, the clp state is defined by each cell, and the decision to discard is evaluated upon receiving each cell. the minimum resource counter vcclp0cnt increments/decrements based on the cell clp received/transmitted. non-user cells always have cell discard congestion rules applied, regardless of the original vc?s congestion setting. non-user cells do not have per-vc congestion as the vcqclp01cnt is not active when a non-user cell is encountered. 10.9.4.3 fcq discard figure 19 - fcq discard rules classclp1thrsh classclp0thrsh classmaxthrsh portmaxthrsh per-class per-port vcclp1thrsh portclp1thrsh portclp0thrsh dirmaxthrsh per-direction dirclp1thrsh dirclp0thrsh per-vc vcclp0thrsh invoke frame discard when portcnt >= portmaxthrsh invoke frame discard when classcnt >= classmaxthrsh invoke frame discard when vccnt >= vcclp0thrsh no discard invoke frame discard on clp1 frame when xxcnt >= xxclp1thrsh invoke frame discard on clp0, clp1 frame when xxcnt >= xxclp0thrsh except clp0 frame having vcclp0cnt < vcclp0minthrsh invoke frame discard when dircnt >= dirmaxthrsh invoke frame discard when freecnt = 0 initial state of freecnt per-device
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 83 when fcq discard is selected, the discard mechanism uses the aal5 eom pti field indicator to delineate frame boundaries. frame discard is evaluated after receiving each cell. the per-vc context parameter, vcgfrmode, dictate how frame discard is evaluated. when vcgfrmode = 0, frame discard is based on the or clp. when vcgfrmode = 1, frame discard is based on the bom clp. the minimum resource counter is incremented/decremented after receiving/transmitting a cell that has the bom clp = 0. when frame discard is invoked, the minimum resource count value will be reduced by the number of cells found in the vc queue if the bom clp = 0. 10.9.5 statistics there are two transmit counts, and three discard counts. all counts are 32-bits wide. the sum of all counts equals the total number of cells received by the s/uni-apex-1k800. table 11 gives a summary of the statistical counts. table 11 - statistical counts count scope description vcclp0txcnt per- vc per-vc count of all cells transmitted that had an outbound clp state of zero. oam cells re-directed to the up will not be represented by this count. vcclp1txcnt per- vc per-vc count of all cells transmitted that had an outbound clp state of one. oam cells re-directed to the up will not be represented by this count. clp0discardcnt global global count of all inbound clp0 cells discarded due to congestion, re-assembly maximum length limit, or zero length check. there is an associated register that holds the last ici that caused this count to increment. clp1discardcnt global global count of all inbound clp1 cells discarded due to congestion, re-assembly maximum length limit, or zero length check. there is an associated register that holds the last ici that caused this count to increment. discardcnt global global count of all discards that are not due to congestion. these include cells discarded due re- assembly time outs, cells received on vcs that were not
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 84 count scope description enabled, execution of a vc queue or a class queue tear down. the definition of the in/out bound clp state is a function of the congestion discard mode, and the per-vc parameter vcgfrmode. table 12 illustrates the definition of in/out bound clp state. table 12 - in/out bound clp state for statistical counts congestion mode vcgfrmode inbound clp outbound clp cell discard x cell clp cell clp 0 cell clp cell clp epd/ppd discard 1 bom clp cell clp 0 or clp cell clp fcq discard 1 bom clp cell clp the table below give a brief summary of the rules applied for discard, and clp definition for incrementing various counts as a function of the discard mode and the specific cell encountered. table 13 - congestion rule & count summary discard mode cell epd/ppd fcq vcgfrmodexxx01xx01 condition cell type x pass thru oam redir ect oam user user pass thru oam redir ect oam user user when discard decision is made cell cell cell bom bom cell cell cell cell rules for discard clp def?n cell cell cell bom bom cell cell or bom vcclp0cnt cell cell n/a cell bom cell n/a bom bom clp definition for various counts vcclp0txcnt or vcclp1txcnt cell cell cell cell cell cell cell cell cell
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 85 discard mode cell epd/ppd fcq vcgfrmodexxx01xx01 condition cell type x pass thru oam redir ect oam user user pass thru oam redir ect oam user user condition clp0discardcnt or clp1discardcnt cell cell cell cell bom cell cell or bom one reads the table vertically. take the last column. a user cell arrives in a connection configured for fcq, vcgfrmode = 1, will have -its discard decision made on a cell by cell basis; -the clp is defined by the bom for discard purposes; -the minimum clp0 count will be incremented based on the bom, if the frame is not discarded; -either vcclp0txcnt or vcclp1txcnt will be incremented based on the clp of the cell, if the frame is not discarded; --either clp0discardcnt or clp1discardcnt will be incremented based on the clp of the bom, if the frame is discarded. 10.9.6 microprocessor queue buffer re-allocation/tear down the microprocessor has the option of engaging one of two macros that provide a fast mechanism to tear down either a vc queue or a class queue for non- shaped port class. specified and initiated through registers, the macro will go to the specified queue, reclaim the buffers in the queue, and reset the appropriate congestion counters. the number of cells that were in the queue are added to the general discard count. the vc queue or class queue remain enabled after the re-allocation. invoking of these functions may reduce general throughput of the device. 10.10 context memory ssram interface the context memory ssram interface stores and retrieves context data from one of two ssram devices: pipelined zbt or register-to-register late write. up to 4 banks and 4 ssram devices are supported, with 1m addressing capability for a total of 4mb data capacity. 2 parity bits are provided to protect the 34-bit data bus. if a parity error occurs, an interrupt is sent to the microprocessor.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 86 the clock source drawn in figure 20 must all be skew aligned at between s/uni- apex-1k800, sdram & ssram clock input pins. figure 20 - 1 bank configuration for 1mb of zbt ssram cmrwb cmceb cma[17:0] cmd[16:0] cmp[0] addr/ctrl data[17:0] cmd[33:17] cmp[1] 256kx18 clk ce2# ce2 addr/ctrl data[17:0] 256kx18 1 0 clk ce2# ce2 clock source to sdram sysclk
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 87 figure 21 - 1 bank of 1mb of late write ssram (2 x 256k*18) cmrwb cma[17:0] cmd[16:0] cmp[0] addr/ctrl data[17:0] cmd[33:17] cmp[1] 256kx18 clk ss# addr/ctrl data[17:0] 256kx18 clk ss# cmceb clock source to sdram sysclk figure 22 - 1 bank of 1mb of late write ssram (1 x 256k*36) cmrwb cma[17:0] a ddr/ctrl data[35:0] cmd[35:0] cmp[1:0] 256kx36 clk ss# cmceb clock to sdra m sysclk
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 88 figure 23 - 2 bank configuration for 2mb of zbt ssram cmrwb cmceb cma[17:0] cmd[16:0] cmp[0] addr/ctrl data[17:0] cmd[33:17] cmp[1] 256kx18 cma[18] addr/ctrl data[17:0] 256kx18 addr/ctrl data[17:0] 256kx18 addr/ctrl data[17:0] 256kx18 10 clock source to sdram clk ce2# ce2 clk ce2# ce2 clk ce2# ce2 clk ce2# ce2 sysclk
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 89 figure 24 - 2 bank configuration for 2mb of late write ssram cmrwb cma[18:1] cmd[16:0] cmp[0] addr/ctrl data[17:0] cmd[33:17] cmp[1] 256kx18 cmab[18] clk ss# addr/ctrl data[17:0] 256kx18 addr/ctrl data[17:0] 256kx18 addr/ctrl data[17:0] 256kx18 cmab[17] clk ss# clk ss# clk ss# cma[0] cmceb nc clock source to sdram sysclk there are two processes, arbitrated by the ssram arbiter, that access the context ssram: 1. the queue engine, for reading and writing context information, and for executing the re-assembly watchdog, described in the aal5 re-assemble queuing section; 2. the microprocessor interface, for reading or writing context information, including the option of mask writes. see the memory port section for a description of the ssram access via the microprocessor interface.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 90 10.11 cell buffer sdram interface the s/uni-apex-1k800 uses the external sdram to buffer queued cells. the cell buffer sdram interface permits up to 2 devices in parallel, with 4m addressing capability for a total of 16 mb of storage, sufficient for up to 256k cells. it has a 32-bit wide data bus, with crc-16 checking applied on a per-cell basis. each cell takes up 64 bytes of memory. the crc-16 is applied to the first 60 bytes. if an error occurs, an interrupt is sent to the microprocessor. the following diagram shows the cell storage map with the 64-byte memory boundary. figure 25 - cell storage map header1 payload1 31 16 15 0 1 2 3 ... 13 15 header2 header3 header4 payload2 payload3 payload4 payload5 payload6 payload7 payload8 reserved (0) payload46 payload47 payload48 31 16 15 0 87 24 23 ... 0 14 crc-16 payload45 reserved (0) reserved (0) xx_addr[17:0] + word # bit # the clock source drawn in figure 26 must all be skew aligned at between s/uni- apex-1k800, sdram & ssrams clock input pins. the following diagrams illustrate the various configurations supported:
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 91 figure 26 - 4 mb ? 64k cells cke clk addr/ctrl dqm[1:0] dq[15:0] 2 x 2k x 256 x 16 1 1 cke clk addr/ctrl dqm[1:0] dq[15:0] 2 x 2k x 256 x 16 clock source sysclk cbcsb cbrasb cbcasb cbweb cbbs[0] cba[10:0] cbdqm[0] cbdq[15:0] cbdqm[1] cbdq[31:16] to ssram figure 27 - 8 mb ? 128k cells sysclk cbcsb cbrasb cbcasb cbweb cbbs[1:0] cba[10:0] cbdqm[1:0] cbdq[31:0] cke clk addr/ctrl dqm[3:0] dq[31:0] 4 x 2k x 256 x 32 1 clock source to ssram
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 92 figure 28 - 16 mb ? 256k cells cke clk addr/ctrl dqm[1:0] dq[15:0] 4 x 4k x 256 x 16 1 1 cke clk addr/ctrl dqm[1:0] dq[15:0] 4 x 4k x 256 x 16 clock source sysclk cbcsb cbrasb cbcasb cbweb cbbs[1:0] cba[11:0] cbdqm[0] cbdq[15:0] cbdqm[1] cbdq[31:16] to ssram there are three processes, arbitrated by the sdram arbiter, that access the cell buffer sdram: 1. the queue engine, for reading and writing cells. the granularity of access by the queue engine is a concatenated 1 cell write - 1 cell read. either the write or the read may not be performed, depending on the queue engine?s requirements; 2. the microprocessor interface, for diagnostic reading or writing of 64 bytes of data. this data is aligned with the cell data. see the operations section for a description of the data format; 3. the refresh controller, which has a programmable refresh rate. the sdram interface will perform the initialization sequence for the sdram. this sequence is triggered by the sdram enable bit cben. the sequence will program the sdram with a cas latency of 3, sequential access, write burst mode, and a burst length of 8. application should ensure that sufficient time is provided between sdram power-up and when this enable bit is set.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 93 the sdram interface, under the direction of the queue engine, performs the header remapping function as the cell is read from sdram. it also attaches the cell prepends including the switch tag, eci/ici and any phy address prepend. 10.12 jtag test access port the jtag test access port block provides jtag support for boundary scan. the standard jtag extest, sample, bypass, idcode and stctest instructions are supported. the s/uni-apex-1k800 identification code is 073260cd hexadecimal.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 94 11 performance 11.1 throughput the maximum throughput is governed at 3 potential bottlenecks: - receive interface configuration. - queue engine mode (shaper on or off). - transmit interface configuration. the lowest throughput of the 3 bottlenecks will dictate the overall throughput for a given cell datapath. general assumptions: sysclk = 80mhz no watch dog recovery in progress sdram refresh set to slowest rate bclk = 66mhz no setup/tear downs/context memory access in progress any-phy clocks = 52mhz 16 bit interface for non up receive and transmit interface ici in hec/udf field for non up receive interface eci and switch tag disabled for non up transmit interface table 14 - receive interface throughput, mcells/sec port/configuration loop wan up assumptions any-phy master 1.67 1.67 n/a address polling range optimized, n external port slaves, n >= 1, equal traffic 1.44 1.44 n/a address polling range set to 2, 1 external port slave utopia l2 master 1.74 1.74 n/a address polling range optimized, n external port slaves, n >= 2, equal traffic utopia l1 master 1.74 1.74 n/a none utopia l2 slave 1.74 1.74 n/a none
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 95 port/configuration loop wan up assumptions up full cell insertion n/a n/a 1.1 sarrxdata0->13 written up partial cell (multi-cast) n/a n/a 1.74 sarrxdata0, 13 written table 15 - queue engine throughput, mcells/sec configuration assumptions shaper disabled 1.74* none shaper enabled 1.42 none * throughput drops down to 1.63 mcells/sec if only a single wan port is transmitting and no cells are being received by either the loop, wan or up rx interfaces. table 16 - transmit interface throughput, mcells/sec port/configuration loop wan up assumptions 0.56* n/a n/a limit 1 cell/port in fifo, 1 external port slave 1.11* n/a n/a limit 2 cell/port in fifo, 1 external port slave 1.0* n/a n/a limit 1 cell/port in fifo, 2 external port slave 1.6* n/a n/a limit 2 cell/port in fifo, 2 external port slave n/a 1.74 n/a 1 external port slave any-phy master n/a 1.68 n/a 2 external port slave, equal traffic 0.61 n/a n/a limit 1 cell/port in fifo, 1 external port slave 1.25 n/a n/a limit 2 cell/port in fifo, 1 external port slave 1.1 n/a n/a limit 1 cell/port in fifo, 2 external port slave utopia l2 master 1.6 n/a n/a limit 2 cell/port in fifo, 2 external port slave
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 96 port/configuration loop wan up assumptions n/a 1.44 n/a 1 external port slave n/a 1.68 n/a 2 external port slave, equal traffic utopia l1 master 1.67 1.74 n/a none utopia l2 slave 1.67 1.74 n/a none up full cell extraction n/a n/a 1.61 none * throughput reduced when shaper is enabled. guarantee minimum 0.4 mcells/sec per loop port when there are 3 or less active loop ports. 11.2 latency the latency that a cell assumes an empty queue, sysclk = 80mhz, any-phy clocks = 52mhz, measure from sop of the any-phy wan/loop receive interface to the sop any-phy wan transmit interface minimum latency = 2340ns. 11.3 cdv there are many points in the s/uni-apex-1k800 where cdv can be introduced.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 97 12 register please use the list of registers as a reference for the register map. notes on register bits: 1. writing values into unused register bits has no effect. however, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. 2. writable normal mode register bits are cleared to logic zero upon reset unless otherwise noted. 3. writing into read-only normal mode register bit locations does not affect s/uni-apex-1k800 operation unless otherwise noted. 4. certain register bits are reserved. these bits are associated with megacell functions that are unused in this application. to ensure that the s/uni-apex- 1k800 operates as intended, reserved register bits must be written with their default value as indicated by the register bit description. 5. s/uni-apex-1k800 is addressable on a long-word basis only. data fields are loaded into s/uni-apex-1k800 registers as described in each specific register section. s/uni-apex-1k800 does not perform any byte swapping. 6. with the exception of the cbi register port, part of the rambist, and the reset and identity register, all registers are inaccessible until the software reset bit in the reset and identity register is removed.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 98 12.1 general configuration and status register 0x00: reset and identity bit type function default 31:8 unused 0 7r/wreset 1 6:4 r type[2:0] 001 3:0 r id[3:0] 0 id[3:0] the id bits can be read to provide a binary number indicating the s/uni- apex-1k800 feature version. these bits are incremented only if features are added in a revision of the chip. type[2:0] the type bits can be read to distinguish the s/uni-apex-1k800 from the other members of the dslam family of devices. reset the reset bit allows the s/uni-apex-1k800 to be reset under software control. if the reset bit is a logic one, the entire s/uni-apex-1k800 except for the microprocessor interface is held in reset. this bit is not self- clearing. therefore, a logic zero must be written to bring the s/uni-apex- 1k800 out of reset. holding the s/uni-apex-1k800 in a reset state places it into a low power, stand-by mode. a hardware reset sets the reset bit, thus negating the software reset. notes: 1) software should ensure that the dllrun in the cbi register port reads back a 1 before releasing the s/uni-apex-1k800 from reset. 2) software should wait 2 clock periods of the slowest clock (wtclk, wrclk, ltclk, lrclk, sysclk) before attempting to write to any other register. exception to this rule is the cbi register port.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 99 register 0x10: hi priority interrupt status register bit type function default 31 r/w reserved 0 30:15 unused 14 r/w wtcellxferr 0 13 r/w wrruntcellerr 0 12 r/w wrparerr 0 11 unused 0 10 r/w ltcellxferr 0 9 r/w lrruntcellerr 0 8 r/w lrparerr 0 7:5 unused 0 4 r/w qfreecntzeroer r 0 3:2 unused 0 1 r/w ssramparerr 0 0 r/w sdramcrcerr 0 each bit in the register is masked with the high priority interrupt mask register. the results are then nor?d together to produce the state of inthib pin. all bits are cleared when this register is read. all may be set to one by the microprocessor for interrupt testing. note that if the interrupt condition persists, the associated status bit will be reasserted. sdramcrcerr this bit goes high when a crc-16 error was detected during a transaction on the sdram interface. ssramparerr this bit goes high when a parity error was detected during a transaction on the ssram interface. qfreecntzeroerr this bit goes high when the entire device is completely congested, and that there is no more memory left to accept one more cell.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 100 lrparerr loop receive parity error detected. lrruntcellerr loop receive runt cell error detected. a sop is detected prior to receiving enough bytes for a cell. ltcellxferr loop transmit cell transfer error was encountered. this interrupt status is asserted when an external master device selects the loop transmit interface for a cell transfer when the fifo is empty. wrparerr wan receive parity error detected. wrruntcellerr wan receive runt cell error detected. a sop is detected prior to receiving enough bytes for a cell. wtcellxferr wan transmit cell transfer error was encountered. this interrupt status is asserted when an external master device selects the wan transmit interface for a cell transfer when the fifo is empty.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 101 register 0x14: high priority interrupt mask bit type function default 31:0 r/w mask[31:0] ffffffff mask[31:0] these bits mask the high priority interrupt status register.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 102 register 0x18: low priority interrupt error register bit type function default 31 r/w reserved 0 30 r/w qshp3ictrerr 0 29 r/w reserved 0 28 r/w qshp2ictrerr 0 27 r/w reserved 0 26 r/w qshp1ictrerr 0 25 r/w reserved 0 24 r/w qshp0ictrerr 0 23 r/w qdirmaxthrsherr 0 22 r/w qportmaxthrsherr 0 21 r/w qclassmaxthrsherr 0 20 r/w qvcmaxthrsherr 0 19 unused 0 18 r/w qcellrxerr 0 17 r/w qvcreaslenerr 0 16 r/w qvcreastimeerr 0 15:0 unused 0 each bit in the register is masked with the low priority interrupt mask register. the results are then nor?d together with the other low priority interrupt register to produce the state of intlob pin. all parameters are cleared when this register is read. all parameters may be set to one by the microprocessor for interrupt testing. qvcreastimeerr watch dog found a re-assembled vc that timed out. the misc error context structure vcreaslenerrici parameter has been updated to indicate the ici of the frame that encountered this error. all cells in the re-assembly queue have been re-allocated. the next cell to arrive will be considered the bom.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 103 qvcreaslenerr maximum length in the re-assembly queue has been encountered. the misc error context structure vcreaslenerrici parameter has been updated to indicate the ici of the frame that encountered this error. all cells in the re- assembly queue have been re-allocated. ppd has been invoked on the vc. qcellrxerr status bit indicating that a cell was received on a vc that was not enabled. caused when either vcen, classen or porten are not set in the context record. the misc error context structure cellrxerrici parameter has been updated to indicate the ici of the cell that encountered this error. qvcmaxthrsherr status bit indicating that a vc has reached the vc maximum threshold of vcmaxthrsh. the maximum congestion id misc context structure vcmaxthrsherrici parameter has been updated to indicate the ici of the cell that encountered this error. qclassmaxthrsherr status bit indicating that a class queue has reached the class maximum threshold classmaxthrsh. the maximum congestion id misc context classmaxthrsherrid & classmaxthrsherrportid parameters have been updated to indicate the port and class of the cell that encountered this error. qportmaxthrsherr status bit indicating that a port queue has reached the port maximum threshold portmaxthrsh. the maximum congestion id misc context structure portmaxthrsh parameter has been updated to indicate the portid of the cell that encountered this error. qdirmaxthrsherr status bit indicating that the per-direction maximum congestion threshold has be encountered. check loopcnt and wancnt in the overall count misc context to determine whether it was the loop or the wan ports that reached this threshold. qshpnictrerr, n = 0..3 status bit indicating that the ingress counter has saturated.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 104 register 0x1c: low priority interrupt error mask bit type function default 31:0 r/w mask[31:0] ffffffff mask[31:0] these bits mask the low priority interrupt status register.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 105 register 0x20: low priority interrupt status register bit type function default 31:7 unused 0 6 r mpidlestatus 1 5 r sarrxemptystatus 1 4 r sarrxrdystatus 1 3:0 r sartxrdystatus[3:0] 0 each bit in the register is masked with the low priority interrupt status mask register. the results are then nor?d together with the other low priority interrupt register to produce the state of intlob pin. sartxrdystatus[3:0] status bit indicating that one of four sar read buffers contains a least one cell for reading. warning : software should not attempt to read this status or clear the associated interrupt mask immediately after extracting a cell from the s/uni-apex-1k800. there is a latency of 3 bclks + 2 sysclks between the last word of a cell read out and this signal going inactive. removing the mask prematurely may generate an unintentional interrupt. sarrxrdystatus status bit indicating that sar receive buffer is ready to accept the next cell. sarrxemptystatus status bit indicating that sar receive buffer is empty. typically used for diagnostic writes. warning : software should not attempt to read this status or clear the associated interrupt mask immediately after injecting a cell into the s/uni- apex-1k800. there is a latency of 5 sysclks between the last word of a cell written out and this signal going inactive. removing the mask prematurely will generate an unintentional interrupt. mpidlestatus status bit indicating the memory port is idle and ready to accept a new command. this signal is the inverse of mpbusy found in the memory port control register.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 106 register 0x24: low priority interrupt status mask bit type function default 31:0 r/w mask[31:0] ffffffff mask[31:0] these bits mask the low priority interrupt status register.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 107 12.2 loop cell interface register 0x100: loop cell rx interface configuration bit type function default 31:18 unused 0 17:16 r/w looprxicisel[1:0] 0 15:13 unused 0 12:8 r/w looprxpolladdr[4:0] 0 7 r/w looprxparpolarity 0 6 r/w looprx8biten 0 5 r/w looprxhecdis 0 4 unused 0 3 r/w looprxicipreen 1 2:1 r/w looprxmode[1:0] 0 0 r/w looprxen 0 all parameters in this register should only be set once at the same time the interface is enabled. once the interface is set, none of these parameters may be changed. looprxen the looprxen enables the loop receive interface. when set to one, the loop receive any-phy interface operates normally. once set, this bit should not be reset to zero. looprxmode[1:0] selects the receive interface mode looprxmode[1:0] operation 00 utopia l2 master, supports 32 phys 01 utopia l1 master, supports 1 phy 10 any-phy master mode inband port notification via the address prepend. supports 32 phys. 11 utopia l2 slave
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 108 looprxicipreen: when set to one, the default, an ici prepend (word 1 in figure 4, byte 1&2 in figure 5) is expected on this interface. when reset to zero an ici prepend is not expected on this interface. when in 8 bit mode, this bit must be set to 1. looprxhecdis when reset to zero, the hec/udf field (word 4 in figure 4, byte 7 in figure 5) is expected on this interface. when set to a one an hec/udf field is not expected on this interface. looprx8biten when reset to zero, this bit sets the interface bus width to 16 bits. when set to one, this bit sets the interface bus width to 8 bit. looprxparpolarity when reset to zero, the loop receive parity is odd. when set to one, the loop receive parity is even. looprxpolladdr[4:0] in utopia l2 slave mode: the five bit utopia address to which the slave will respond. in any-phy and utopia l2 master mode: these bits represents the polling address range. looprxpolladdr[4:0] polling range 0-2 not valid 3 address 3->0 ?? 31 address 31->0 in utopia l1 master mode: these bits are reserved. looprxicisel[1:0] indicates which part of the incoming cell, the internal ici is selected from: loopicisel[1:0] source 00 user prepend (note: looprxicipreen must be set). 01 vpi/vci fields: if the vpi < ?fff? then
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 109 ici = ?0? & vpi; -- this connection is a vpc connection., -- vpi cannot be set to a value larger than "3ff" else ici = "0" & vci; -- this connection is a vcc connection. -- vci cannot be set to a value larger than "3ff" end if; 10 hec/udf fields (note: both looprxhecdis and looprx8biten must be clear, and not valid for 8-bit mode). 11 unused
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 110 register 0x104: loop cell tx interface configuration bit type function default 31 r looptxpffullstatus 0 30:29 unused 0 28:24 r/w looptxpfthres 0 23:22 unused 0 21 r/w looptxtwocellen 0 20 r/w looptxschen 0 19:13 unused 0 12:8 r/w looptxslaveaddr[4:0] 0 7 r/w looptxparpolarity 0 6 r/w looptx8biten 0 5 r/w looptxhecdis 0 4 r/w looptxswitchpreen 0 3 r/w looptxecipreen 1 2:1 r/w looptxmode[1:0] 0 0 r/w looptxen 0 all parameters in this register should only be set once at the same time the interface is enabled. once the interface is set, none of these parameters may be changed. looptxen the looptxen enables the loop transmit interface. when set to one, the loop transmit any-phy interface operates normally. once set, this bit should not be reset to zero. looptxmode[1:0] selects the transmit interface mode. looptxmode[1:0] operation 00 utopia l2 master mode, supports 32 phys 01 utopia l1 master mode, supports 1 phy
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 111 looptxmode[1:0] operation 10 any-phy master mode inband port selection, via the address prepend. supports 128 phys. 11 utopia l2 slave
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 112 looptxecipreen: when reset to zero, a eci prepend (word 2 in figure 6, byte 3&4 in figure 7) is not present on this interface. when set to one a eci prepend is present on this interface. looptxswitchpreen when reset to zero, a switch tag prepend (word 1 in figure 6, byte 1&2 in figure 7) is not present for this interface. when set to a one a switch tag is present for this interface. looptxhecdis when reset to zero, the eci is generated on the hec/udf field (word 5 in figure 6, byte 9 in figure 7) in this interface. when set to a one an hec/udf field is not generated on this interface. looptx8biten when reset to zero, this bit sets the interface bus width to 16 bits. when set to one, this bit sets the interface bus width to 8 bit. looptxparpolarity when reset to zero, the loop transmit parity is odd. when set to one, the loop transmit parity is even. looptxslaveaddr[4:0] the five bit utopia address to which the slave will respond. used only when the loop tx interface is configured for utopia l2 slave. looptxschen the looptxschen enables the loop port scheduler for normal operation. the looptxschen enable should be set to a ?1? for normal operation after the initialization of the loop?s class not empty context memory. looptxtwocellen when set to 0, the loop port scheduler will allow a maximum one cell per port in the transmit pipeline for each ltpa. when set to 1, the loop port scheduler will allow a maximum of two cells per port in the transmit pipeline for each ltpa. looptxpfthres[4:0] controls the depth of the poll request fifo, offset by 1. a value of 0 represents poll depth of 1. recommended value is 0x1f.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 113 looptxpffullstatus read only bit. when read high, it indicates that the polling fifo has reached the looptxpfthres value. reading this bit will reset the value to zero. used for diagnostics. 12.3 wan cell interface register 0x200: wan cell rx interface configuration bit type function default 31:18 unused 0 17:16 r/w wanrxicisel[1:0] 0 15:13 unused 0 12:10 r/w reserved 0 9:8 r/w wanrxpolladdr[1:0] 0 7 r/w wanrxparpolarity 0 6 r/w wanrx8biten 0 5 r/w wanrxhecdis 0 4 unused 0 3 r/w wanrxicipreen 1 2:1 r/w wanrxmode[1:0] 0 0 r/w wanrxen 0 all parameters in this register should only be set once at the same time the interface is enabled. once the interface is set, none of these parameters may be changed. wanrxen the wanrxen enables the wan receive interface. when set to one, the wan receive any-phy interface operates normally. once set, this bit should not be reset to zero. wanrxmode[1:0] controls the port selection mode. wanrxmode[1:0] operation 00 utopia l2 master, supports 4 phys
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 114 wanrxmode[1:0] operation 01 utopia l1 master, supports 1 phy 10 any-phy master mode inband port notification via the address prepend. supports 4 phys. 11 utopia l2 slave wanrxicipreen when set to one, the default, an ici prepend (word 1 in figure 4, byte 1&2 in figure 5) is expected on this interface. when reset to zero an ici prepend is not expected on this interface. when in 8-bit mode, this bit must be set to 1. wanrxhecdis when reset to zero, the hec/udf field (word 4 in figure 4, byte 7 in figure 5) is expected on this interface. when set to a one an hec/udf field is not expected on this interface. wanrx8biten when reset to zero, this bit sets the interface bus width to 16 bits. when set to one, this bit sets the interface bus width to 8 bit. wanrxparpolarity when reset to zero, the wan receive parity is odd. when set to one, the wan receive parity is even. wanrxpolladdr[1:0] in utopia l2 slave mode: the two bit utopia address to which the slave will respond. in any-phy and utopia l2 master mode: these bits represents the polling address range. wanrxpolladdr[1:0] polling range 0-2 not valid 3 address 3->0 in utopia l1 master mode: these bits are reserved. wanrxicisel[1:0] indicates which part of the incoming cell, the internal ici is selected from:
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 115 wanrxicisel[1:0] source 00 user prepend (note: wanrxicipreen must be set). 01 if the vpi < ?fff? then ici = ?0? & vpi; -- this connection is a vpc connection., -- vpi cannot be set to a value larger then "3ff" else ici = "0" & vci; -- this connection is a vcc connection. -- vci cannot be set to a value larger then "3ff" end if; 10 hec/udf fields (note: both wanrxhecdis and wanrx8biten must be clear, and not valid for 8-bit mode). 11 unused
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 116 register 0x204: wan cell tx interface configuration bit type function default 31:30 r/w wantx3portid[1:0] 3 29:28 r/w wantx2portid[1:0] 2 27:26 r/w wantx1portid[1:0] 1 25:24 r/w wantx0portid[1:0] 0 23:21 unused 0 20 r/w wantxschen 0 19:10 unused 0 9:8 r/w wantxslaveaddr[1:0] 0 7 r/w wantxparpolarity 0 6 r/w wantx8biten 0 5 r/w wantxhecdis 0 4 r/w wantxswitchpreen 0 3 r/w wantxecipreen 1 2:1 r/w wantxmode[1:0] 0 0r/w wantxen 0 all parameters in this register should only be set once at the same time the interface is enabled. with the exception of the wantxxportid and wantxslaveaddr bits, once the interface is set, none of these parameters may be changed. wantxen the wantxen enables the wan transmit interface. when set to one, the wan transmit any-phy interface operates normally. once set, this bit should not be reset to zero. wantxmode[1:0] controls the port selection mode. wantxmode[1:0] operation 00 utopia l2 master, supports 4 phys 01 utopia l1 master , supports 1 phy
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 117 wantxmode[1:0] operation 10 any-phy master mode inband port notification via the address prepend. supports 4 phys. 11 utopia l2 slave wantxecipreen when reset to zero, an eci prepend (word 2 in figure 6, byte 3&4 in figure 7)is not generated on this interface. when set to one an eci prepend is generated on this interface. wantxswitchpreen when reset to zero, a switch tag prepend (word 1 in figure 6, byte 1&2 in figure 7) is not generated for this interface. when set to a one a switch tag prepend is generated for this interface. wantxhecdis when reset to zero, the eci is generated on the hec/udf field (word 5 in figure 6, byte 9 in figure 7) in this interface. when set to a one an hec/udf field is not generated on this interface. wantx8biten when reset to zero, this bit sets the interface bus width to 16 bits. when set to one, this bit sets the interface bus width to 8 bit. wantxparpolarity when reset to zero, the wan transmit parity is odd. when set to one, the wan transmit parity is even. wantxslaveaddr[1:0] in utopia l2 slave mode : the two bit utopia address to which the slave will respond. in utopia l1 master mode: the two bit utopia address that is presented during the address selection phase. permits an external utopia l2 slave to be connected when interface is in utopia l1 master mode. wantxschen the wantxschen enables the wan port scheduler for normal operation. the wantxschen enable should be set to a ?1? for normal operation after the initialization of the wan?s class not empty context memory.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 118 wantxxportid[1:0], x = 0..3 representing channel #. the value in these register are the alias mapping of the internal wan portid to the physical port id as presented by the any-phy/utopia master mode interface. by default, the internal matches the external port ids. in slave mode, the wan port scheduler only operates on port 0; therefore, the following relationship must always be true: wantx0portid = wantxslaveaddr warning : the values programmed into these four registers must always be unique. two or more internally active portid must never point to the same active physical port id.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 119 12.4 memory port see section on memory port mapping for specific context parameter definitions. register 0x300: memory port control bit type function default 31 r/w mpbusy 0 30:29 r/w mpcommand[1:0] 0 28 unused 27:24 r/w mplworden[3:0] 0 23:22 r/w mpmemselect[1:0] 0 21:18 unused 0 17:0 r/w mpquadaddr[17:0] 0 writes to this register will place the microprocessor interface in wait state until the mpbusy bit in the control register is clear. mpquadaddr[17:0] indicates the beginning quad long word address for the operation in memory. up to 4 megabytes of memory is supported in each aperture by this address (or 256k 16-byte regions). mpmemselect[1:0] selects the memory aperture. the aperture is chosen according to the following table. mpmemselect[1:0] aperture selected 00 external queue context 01 internal queue context 10 internal wan port context 11 internal loop port scheduler context mplworden[3:0] indicates which long words of data will be written to or read from memory. this register is used to resolve the quad long word address mpquadaddr down to long word resolution.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 120 for masked writes, only one bit should be set, identifying the long word address. if more than one bit in this parameter is set then the least significant active bit will be used to indicate the long word address to be modified. for normal read/write access, the number of active bits permitted is unrestricted with the exception of the internal wan port scheduler context memory map and internal loop port scheduler context memory map. these 2 memory maps are restricted to having only 1 active bit per access. mpcommand[1:0] selects the type of access. if a masked write is indicated, a 34-bit mask will be used to determine which bits within one long word will be written. mpcommand[1:0] command selected 00 reserved 01 write 10 read 11 masked write mpbusy when set to a one by the microprocessor, the command will be executed. when the command is complete, this bit will be cleared to zero. this signal is the inverse of mpidlestatus found in the interrupt status register.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 121 register 0x340-0x34c: memory write data (burstable) bit type function default 31:0 r/w mpwrdatan[31:0], n = 0..3 0 writes to this register will be delayed until the mpbusy bit in the control register is clear. mpwrdatan[31:0], n = 0..3 the least significant 32 bits of write data to be directed to the address and aperture as specified in the memory port control register. for normal write operations, mpwrdatan corresponds to mplworden[n]. for masked writes, mpwrdata0 contains the data, mpwrdata1 contains the mask bits: only bits set to a one in this vector will be overwritten with mpwrdata0 in memory.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 122 register 0x350: memory write data overflow (burstable) bit type function default 31:8 unused 0 7:6 r/w mpwrdata3[33:32] 0 5:4 r/w mpwrdata2[33:32] 0 3:2 r/w mpwrdata1[33:32 0 1:0 r/w mpwrdata0[33:32] 0 writes to this register will be delayed until the mpbusy bit in the control register is clear. this register is only used for writes to the external queue context. mpwrdata0[33:32] the most significant 2 bits of mpwrdata0. see memory write data array for a more detailed description. mpwrdata1[33:32] the most significant 2 bits of mpwrdata1. see memory write data array for a more detailed description. mpwrdata2[33:32] the most significant 2 bits of mpwrdata2. see memory write data array for a more detailed description. mpwrdata3[33:32] the most significant 2 bits of mpwrdata3. see memory write data array for a more detailed description.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 123 register 0x380-0x38c: memory read data (burstable) bit type function default 31:0 r mprddatan[31:0] , n = 0..3 0 reads from this register will be delayed until the mpbusy bit in the control register is clear. mprddatan[31:0], n = 0..3 the least significant 32 bits of read data from the address and aperture as specified in the memory port control register. mprddatan corresponds to mplworden[n].
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 124 register 0x390: memory read data overflow (burstable) bit type function default 31:8 unused 0 7:6 r mprddata3[33:32] 0 5:4 r mprddata2[33:32] 0 3:2 r mprddata1[33:32] 0 1:0 r mprddata0[33:32] 0 reads from this register will be delayed until the mpbusy bit in the control register is cleared. this register is only used for reads from external queue context. mprddata0[33:32] indicates the most significant 2 bits of the first word of read data from memory. see memory read data array for a more detailed description. mprddata0[33:32] indicates the most significant 2 bits of the first word of read data from memory. see memory read data for a more detailed description. mprddata1[33:32] indicates the most significant 2 bits of the second word of read data from memory. see memory read data for a more detailed description. mprddata2[33:32] indicates the most significant 2 bits of the third word of read data from memory. see memory read data for a more detailed description. mprddata3[33:32] indicates the most significant 2 bits of the fourth word of read data from memory. see memory read data for a more detailed description.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 125 12.5 sar 12.5.1 receive in normal sar operation, writing to any sar receive data register when sarrxrdystatus = 0 (in the low priority interrupt status register) will cause the microprocessor bus to be held in wait state. data transfer is initiated when sarrxdata13 is written. when in diagnostic write mode, writing to any sar receive data register when sarrxemptystatus = 0 (in the low priority interrupt status register) will cause the microprocessor bus to be held in wait state. data transfer is initiated when sarrxdata15 is written. register 0x400-0x43c: sar receive data (burstable) bit type function default 31:0 w sarrxdatan[31:0], n = 0..15 x sarrxdata0[15:0]: ici in normal sar operation, this is the ingress connection identifier that identifies the connection in which the cell belongs. in diagnostic write mode, this is simply a write data register. sarrxdata0[17:16]: crc trailer in normal sar operation, these bits define whether the next cell received should be over written with a trailer. sarrxdata0[17:16] function 00 do not overwrite the end of the current cell with a trailer 01 write the current cell with crc-32 trailer. 10 write the current cell with crc-10 trailer. 11 unused in diagnostic write mode, this is simply a write data register. sarrxdata0[18]: crc-32 init in normal sar operation, when set, this bit will set the internal crc32 to 0xffffffff. required when the current cell received is the bom of an
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 126 aal5 packet. this bit must be reset if the current cell received is not the bom of an aal5 packet. in diagnostic write mode, this is simply a write data register. sarrxdata0[31:19] in normal sar operation, these bits are not used. in diagnostic write modes, this is simply a write data register. sarrxdatan[31:0], n=1..15: in normal sar operation, these registers contain the header and payload. data stored in sarrxdata14 & sarrxdata15 are not used. transfer is initiated when sarrxdata13 is written. in diagnostic write mode, this is simply a write data register. transfer is initiated when sarrxdata15 is written.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 127 12.5.2 transmit reading from any registers within the transmit sar when sartxrdystatus = 0(in the low priority interrupt status register), or when sardiagrdbusy = 1 (in the cell buffer diagnostic control register) will cause the microprocessor bus to be held in wait state. all registers in the transmit sar are read-only; the registers may not be initialized by the microprocessor directly. all 16 registers in the class 3 transmit sar buffer are used to report read data when cell buffer diagnostic mode is enabled. in this mode, the entire block of data is cleared from the buffer once the last word is read. register 0x500-0x53c: sar transmit data, class 0 (burstable) register 0x540-0x57c: sar transmit data, class 1 (burstable) register 0x580-0x5bc: sar transmit data, class 2 (burstable) register 0x5c0-0x5fc: sar transmit data, class 3 (burstable) bit type function default 31:0 r sartxdatan[31:0], n = 0..15 x sartxdata0[15:0]: eci in normal sar operation. this is the egress connection identifier of the cell received. in diagnostic read mode, class 3, this is the read data. sartxdata0[16]: crc32 status in normal sar operation, when high, this bit indicates that the aal5 crc32 polynomial check failed. this bit is only valid for cells that belong to an aal5 packet (as indicated by the cell header). within aal5 packets, this status will return the actual crc32 status with the eom, and all other cells will be accompanied by a status of 0. this status should be ignored for all other cell types. in diagnostic read mode, class 3, this is the read data.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 128 sartxdata0[17]: crc10stat in normal sar operation, when high, this bit indicates that the crc10 polynomial check failed. this status is only valid when the cell in the buffer is an oam cell (as indicated by the cell header). this status should be ignored for all other cell types. in diagnostic read mode, class 3, this is the read data. sartxdata0[31:18]: unused in normal sar operation, not used. in diagnostic read mode, class 3, this is the read data. sartxdatan[31:0], n=1..15: in normal sar operation, these registers contain the header and payload. for data stored in sartxdata14 & sartxdata15 are reserved and are not used. a new transfer is initiated when sartxdata13 is read. in diagnostic read mode, class 3, these registers are the read data. a new transfer is initiated when sartxdata15 is read. 12.5.3 cell buffer diagnostic access register 0x600: cell buffer diagnostic control bit type function default 31 r/w sardiagrdbusy 0 30 r/w sardiagrdmodeen 0 29 r sardiagrdmodelock 0 28 r/w sardiagwrmodeen 0 27:18 unused 0 17:0 r/w sardiagaddr[17:0] 0 sardiagaddr[17:0] indicates the beginning 16-long word address for the operation in cell buffer. up to 16 megabytes of memory is supported by this address (or 256k 64-byte regions).
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 129 sardiagwrmodeen when enabled, the sar receive staging buffer will be used as a port to write data directly to the cell buffer (sdram). receiving of normal cells into the traffic stream is no longer possible while this parameter is enabled. this bit should only be set when sarrxemptystatus = 1 in the low interrupt status register. sardiagrdmodelock read only. indicates that the sar is ready to perform a diagnostic reads. a lock will only occur when sardiagrdmodeen = 1, and all non-diagnostic cells remaining in the class 3 tx staging buffers have been read by the microprocessor. sardiagrdmodeen when enabled, normal loading of cells into all 4 classes of the sar tx staging buffers are withheld. a cell that is in the process of being loaded into a tx staging buffer when this bit is set will be allowed to complete. sardiagrdbusy setting this register to one will initiate a diagnostic read from the cell buffer (sdram). when the command is complete, this bit will be cleared to zero. this bit should not be set to one until sardiagrdmodeen = 1, sardiagrdmodelock = 1, and sartxrdystatus = 0. 12.6 queue engine register 0x700: queue context configuration bit type function default 31 r/w qengen 0 30 r qbusy 0 29 r/w qsglstep 0 28:27 unused 0 26 r/w qrxtxarbsel 0 25 unused 0 24 r/w qnumvcsel 0 23:16 r/w qcellstartadr[7: 0] 0 15:8 r/w qlclassstartadr 0
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 130 bit type function default [7:0] 7:0 r/w qshpstartadr[7: 0] 0 qshpstartadr[7:0] defines the memory port starting 4 long word address for traffic shaping records in the ssram context memory. units in k values. warning: this value must not change while the queue engine is enabled. qlclassstartadr[7:0] defines the memory port starting 4 long word address for loop class records in the ssram context memory. units in k values. warning: this value must not change while the queue engine is enabled. qcellstartadr[7:0] defines the memory port starting 4 long word address for cell records in the ssram context memory. units in k values warning: this value must not change while the queue engine is enabled. qnumvcsel qnumvcsel this bit must always be set to "1" qrxtxarbsel selects between 2 arbitration schemes. when qrxtxarbsel = 0, rr is used to select between wan, loop and sar. when qrxtxarbsel = 1, rr is used to select between wan and loop, and sar having low priority. qsglstep forces the queue engine to process the winner of the service arbitration and then halt. when invoked, the register qengen will be set to one. when qbusy returns a one, both qengen and qsglstep will be reset back to zero. to be used only for diagnostics. qbusy status signal indicating that the queue engine is currently active.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 131 qengen the qengen enables the queue engine for normal operation. when qengen = 0 and qbusy = 0, all queue engine operations are disabled. the qengen should be set to a ?1? for normal operation after the initialization of the s/uni-apex-1k800 and the s/uni-apex-1k800?s context memory. this register will reset to zero if qsglstep is invoked.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 132 register 0x704: receive and transmit control bit type function default 31:14 unused 0 13 r/w qlooprxfilter 0 12 r/w qlooprxdis 0 11:10 unused 0 9 r/w qwanrxfilter 0 8 r/w qwanrxdis 0 7:5 unused 0 4 r/w qlooptxdis 0 3:1 unused 0 0 r/w qwantxdis 0 qwantxdis when setting this bit to one, all cell request by the wan transmit interface will be ignored. qlooptxdis when setting this bit to one, all cell request by the loop transmit interface will be ignored. qwanrxdis when setting this bit to one, all cell request by the wan receive interface will be ignored. qwanrxfilter when setting this bit to one, only up destined cells received via the wan receive interface will be serviced. cells destined for the wan or loop will be discarded and the general discard count incremented. used when the device is in redundent mode qlooprxdis when setting this bit to one, all cell request by the loop receive interface will be ignored.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 133 qlooprxfilter when setting this bit to one, only up destined cells received via the loop receive interface will be serviced. cells destined for the wan or loop will be discarded and the general discard count incremented. used when the device is in redundent mode
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 134 register 0x710: max direction congestion thresholds bit type function default 31:24 unused 0 23:16 r/w qloopmaxthrsh [7:0] 0 15:8 unused 0 7:0 r/w qwanmaxthrsh [7:0] 0 this register contains all the maximum per-direction congestion threshold values for the wan and loop ports. please refer to section 14.2 for a complete definition of m bit logarithmic, n bit fractional. qwanmaxthrsh[7:0] sets the maximum threshold for cells destined for all 4 wans combined. 4 bit logarithmic, 4 bit fractional. qloopmaxthrsh[7:0] sets the maximum threshold for cells destined for all 128 loops combined. 4 bit logarithmic, 4 bit fractional.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 135 register 0x714: clp0 direction congestion thresholds bit type function default 31:27 unused 0 23:16 r/w qloopclp0thrs h [7:0] 0 15:8 unused 0 7:0 r/w qwanclp0thr sh [7:0] 0 this register contains all the clp0 per-direction congestion threshold values for the wan and loop ports. please refer to section 14.2 for a complete definition of m bit logarithmic, n bit fractional. qwanclp0thrsh[7:0] sets the epd threshold for clp0 cells destined for all 4 wans combined. 4 bit logarithmic, 4 bit fractional. qloopclp0thrsh[7:0] sets the epd threshold for clp0 cells destined for all 128 loops combined. 4 bit logarithmic, 4 bit fractional.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 136 register 0x718: clp1 direction congestion thresholds bit type function default 31:27 unused 0 23:16 r/w qloopclp1thrs h [7:0] 0 15:11 unused 0 7:0 r/w qwanclp1thr sh [7:0] 0 this register contains all the clp1 per-direction congestion threshold values for the wan and loop ports. please refer to section 14.2 for a complete definition of m bit logarithmic, n bit fractional. qwanclp1thrsh[7:0] sets the epd threshold for clp1 cells destined for all 4 wans combined. 4 bit logarithmic, 4 bit fractional. qloopclp1thrsh[7:0] sets the epd threshold for clp1 cells destined for all 128 loops combined. 4 bit logarithmic, 4 bit fractional.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 137 register 0x71c: re-assembly maximum length bit type function default 31:10 unused 0 9:0 r/w qreasmaxlen[9 :0] 0 qreasmaxlen[9:0] defines the alternate re-assembly maximum length, in cells. when a vc has frame continuous queuing, the vc context parameter vcreasmaxsize = 1, and the vc?s frame length exceeds this register, an epd will be invoked.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 138 register 0x720: watch dog ici patrol range bit type function default 31:26 r/w reserved 0 25:16 r/w qwdendici[9:0] 0 15:10 r/w reserved 0 9:0 r/w qwdstartici[9:0 ] 0 reserved bits [31:26] must always be set to ?0? reserved bits [15:10] must always be set to ?0? qwdstartici[9:0] identifies the first ici to be checked for re-assembly time-outs. warning: this value must not change while a patrol is active. qwdendici[9:0] identifies the last ici to be checked for re-assembly time-outs. warning: this value must not change while a patrol is active.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 139 register 0x724: tear down queue id bit type function default 31:26 r/w unused] 0 25:16 r/w qtdici[9:0] 0 15:11 r/w unused 0 10:4 r/w qtdportid[6:0] 0 3:2 unused 0 1:0 r/w qtdclassid[1:0] 0 qtdclassid[1:0] identifies the class to be torn down from service. used only when tearing down a class. warning: this value must not change while a tear down is active. qtdportid[6:0] identifies the port id of the class queue that is to be torn down from service. used only when tearing down a class. see vc context record for portid encoding. warning: this value must not change while a tear down is active. qtdici[9:0] identifies the vc queue that is to be torn down from service. used only when tearing down a vc. warning: this value must not change while a tear down is active.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 140 register 0x728: watch dog / tear down status bit type function default 31:6 unused 0 5 r/w qtdmode 0 4 r/w(1) qtdactive 0 3:1 unused 0 0 r/w(1) qwdactive 0 qwdactive when setting this bit to one, the watch dog will begin its patrol. when the patrol is over, this bit will reset to zero. this bit cannot be reset to zero by the microprocessor. qtdactive when setting this bit to one, the tear down macro, as defined in the qtdmode, will be initiated. when the macro has completed its tear down, this bit will reset to zero. this bit cannot be reset to zero by the microprocessor. qtdmode when setting this bit to zero, a tear down macro will remove a vc queue, as identified in the tear down queue id register, from service, re-allocate the buffers in the queue, and update the general discard count. when setting this bit to a one, a tear down macro will remove a class queue, as identified in the tear down queue id register, from service, re-allocate the buffers in the queue, and update the general discard count. warning: this value must not change while a tear down is active. warning: 1) tearing down a class queue should only be done after all the vcs within the class has been torn down first. 2) after performing a vc tear down, do not setup another vc until either the class queue has been torn down or drain the class queue until vcclassqclp01cnt = 0. failure to do this will result in anomalies in the new vc, such as inaccurate vc weights (for wfq vcs) and premature discard at the per-vc hierarchical level.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 141 register 0x730: shaper 0 configuration (n = 0) register 0x734: shaper 1 configuration (n = 1) register 0x738: shaper 2 configuration (n = 2) register 0x73c: shaper 3 configuration (n = 3) bit type function default 31 r qshpnexpcong 0 30:29 unused 28:20 r/w qshpnrtrate[8: 0], n = 0..3 0 19:18 unused 0 17:16 r/w qshpnredfact[1 :0] , n = 0..3 0 15:12 r/w qshpnthrshval[ 3:0] , n = 0..3 0 11:8 r/w qshpnmeasint[3: 0] , n = 0..3 0 7:6 r/w qshpnclass[1:0] , n = 0..3 0 5:4 r/w qshpnport[1:0] , n = 0..3 0 3 unused 0 2 r/w qshpnthrshen, n = 0..3 0 1 r/w qshpnslowdow nen, n = 0..3 0 0 r/w qshpnen, 0
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 142 bit type function default n = 0..3 there are four shapers, n = 0..3. each shaper can be assigned to the same port, or can be assigned to different ports. only one shaper may be assigned to any one port/class combination. only wan ports may be shaped. if a port/class combination is to be shaped, the vcqueue parameter defined in the vc context record structure will be overridden. note : if one or more shaper is enabled, then all 4 registers must be programmed with unique port/class combinations. qshpnen, n=0..3 enable for shaper n. warning : this register can only be modified during a port/class setup, and when the queue engine is disabled. qshpnslowdownen, n=0..3 enables the slow down of the time reference clock used by shaper n to calculate transmission events. enabling this feature will provide fair shaping to high speed vcs qshpnthrshen, n=0..3 defines how congestion is to be declared for shaper n. when set to zero, the declaration is based on the comparison between the current class queue length and the number of cells leaving the class queue over the previous measurement period. when set to one, the declaration is based on the comparison between the current class queue length and the qshpthrshval. this register has no effect if qshpnslowdownen = 0. qshpnport[1:0]; n=0..3 wan port that shaper n is linked to. warning : this register can only be modified during a port/class setup, and when the queue engine is disabled.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 143 qshpnclass[1:0], n=0..3 class that shaper n is associated with. warning : this register can only be modified during a port/class setup, and when the queue engine is disabled. qshpnmeasint[3:0], n=0..3 encoded value defining the number of clock cycles over which to measure congestion levels for shaper n. the period defined is not affected by the slow down factor. encoding formula is 64 * 2^m. this register has no effect if qshpnslowdownen = 0. qshpnthrshval[3:0], n=0..3 defines a value for the class queue length threshold value. used to select whether to speed up or slow down the shaper n. effective value = 2 (t+1) ? 1, where t = qshpnthrshval[3:0] this register has no effect if qshpnslowdownen = 0 or qshpnthrshen = 0. qshpnredfact[1:0], n=0..3 encoded value for the slow down rate reduction factor. controls how quickly the shaper n speeds up. low values will produce better fairness at the cost of utilization. qshpnredfact[1:0] effective value 02 14 28 316 this register has no effect if qshpnslowdownen = 0. qshpnrtrate[8:0], n=0..3 real time rate for shaper n. represents the maximum shaped data rate, calculated in the number of clock cycles per timeslot. the sum of all active real time rate must be less than the link rate of 1.42mcells/s. the table below provides the decimal setting for various configurations:
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 144 sysclk (mhz) max. shaped rate qshpnrtrate (decimal) max. active shapers 80 1.42 mcells/s 57 1 80 355 kcells/s 227 4 40 355 kcells/s 114 2 where qshpnrtrate = roundup(sysclk (mhz) / effective data rate). qshpnexpcong, n = 0..3 status bit indicating shaper n has experienced congestion, and that the time slot counter was slowed down. this bit is cleared when this register is read. 12.7 memory interface register 0x800: sdram/ssram configuration bit type function default 31:17 unused 0 16 r/w cmlatewrite 0 15 unused 0 14:8 r/w cbrefdivide[6:0 ] 0 7:1 unused 0 0 r/w cben 0 cben the cben enables the sdram interface. a transition from 0 to 1 initiates the sdram initialization procedures. this enable is provided to ensure that the power-up time before the initialization sequence is applied to the sdram is met. when cben = ?0?, no sdram accesses will take place and the chip will not operate properly. cbrefdivide[6:0] defines the sysclk divide down factor to determine the sdram refresh rate. actual divide down value is the value stored in the register multiplied by 16 decimal, plus 1. for example, a value of 78 decimal will produce a refresh cycle every 78*16 + 1 = 1249 sysclks. a zero value is not permitted.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 145 cmlatewrite the cmlatewrite selects the type of ssram connected. when set to zero, pipelined zbt ssram is configured. when set to one, register to register late write ssram is configured. when late write is selected, pins cmab[18] & cmab[17] change functionality and become the chip enable bar for odd and even addresses, respectively. 12.8 cbi interface register 0xa00: cbi register port bit type function default 31 r/w cbibusy 0 30 r/w cbirdwrb 0 29:16 unused 0 15:14 r/w cbiaddr[1:0] 0 13 r/w cbitrsb 0 12 unused 0 11 r/w cbitstb 1 10:8 unused 0 7:0 r/w cbidata[7:0] 0 writes to this register will place the microprocessor interface in wait state until the cbibusy bit is clear. cbidata[7:0] data value used to write into the cbi port or read from the cbi port. address specified by cbiaddr[2:0] cbitstb active low signal used during production testing. normally set high. cbiaddr[1:0] address bus used to select the cbi register.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 146 cbitrsb test select bit. should always be set to 1 during normal mode access. cbirdwrb defines whether a read or write to the cbi register is to be performed. when set to 0, a write command is defined. when set to 1 a read command is defined. command invoked when cbibusy is set to 1. cbibusy when set to a one, the cbirdwrb command will be executed. when the command is complete, this bit will be cleared to zero.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 147 13 cbi register port mapping cbi register 0x00: configuration bit type function default bit 7 unused x bit 6 unused x bit 5 r/w reserved 0 bit 4 r/w override 0 bit 3 unused x bit 2 r/w errore x bit 1 r/w vern_en 0 bit 0 r/w lock 0 the dll configuration register controls the basic operation of the dll. lock: the lock register is used to force the dll to ignore phase offsets indicated by the phase detector after phase lock has been achieved. when lock is set to logic zero, the dll will track phase offsets measured by the phase detector between the sysclk and the refclk inputs. when lock is set to logic one, the dll will not change the tap after the phase detector indicates of zero phase offset between the sysclk and the refclk inputs for the first time. vern_en: the vernier enable register (vern_en) forces the dll to ignore the phase detector and use the tap number specified by the vernier[7:0] register bits. when vern_en is set to logic zero, the dll operates normally adjusting the phase offset based on the phase detector. when vern_en is set to logic one, the delay line uses the tap specified by the vernier[7:0] register bits. used only for diagnostics. errore: the error interrupt enable (errore) bit enables the error indication interrupt. when errore is set high, an interrupt is generated upon assertion event of the err output and error register. when errore is set low, changes in the error and err status do not generate an interrupt.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 148 override: the override control (override) disables the dll operation. when override is set low, the dll generates the dllclk by delaying the sysclk until the rising edge of refclk occurs at the same time as the rising edge of sysclk. when override is set high, the dllclk output is a buffered version of the sysclk input. used only for diagnostics.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 149 cbi register 0x01: vernier control bit type function default bit 7 r/w vernier[7] 0 bit 6 r/w vernier[6] 0 bit 5 r/w vernier[5] 0 bit 4 r/w vernier[4] 0 bit 3 r/w vernier[3] 0 bit 2 r/w vernier[2] 0 bit 1 r/w vernier[1] 0 bit 0 r/w vernier[0] 0 the vernier control register provides the delay line tap control when using the vernier option. used only for diagnostics. vernier[7:0]: the vernier tap register bits (vernier[7:0]) specifies the phase delay through the dll when using the vernier feature. when vern_en is set high, the vernier[7:0] registers specify the delay tap used. when vern_en is set low, the vernier[7:0] register is ignored. a vernier[7:0] value of all zeros specifies the delay tap with the minimum delay through the delay line. a vernier[7:0] value of 255 specifies the delay tap with the maximum delay through the delay line.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 150 cbi register 0x02: delay tap status bit type function default bit 7 r tap[7] x bit 6 r tap[6] x bit 5 r tap[5] x bit 4 r tap[4] x bit 3 r tap[3] x bit 2 r tap[2] x bit 1 r tap[1] x bit 0 r tap[0] x the dll delay tap status register indicates the delay tap used by the dll to generate the outgoing clock. writing to this register performs a software reset of the dll. a software reset requires a maximum of 24*256 sysclk cycles for the dll to regain lock. during this time the dllclk phase is adjusting from its current position to delay tap 0 and back to a lock position. used only for diagnostics. tap[7:0]: the tap status register bits (tap[7:0]) specifies the delay line tap the dll is using to generate the outgoing clock dllclk. when tap[7:0] is logic zero, the dll is using the delay line tap with minimum phase delay. when tap[7:0] is equal to 255, the dll is using the delay line tap with maximum phase delay. tap[7:0] is invalid when vernier enable vern_en is set to one.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 151 cbi register 0x03: control status bit type function default bit 7 r sysclki x bit 6 r refclki x bit 5 r errori x bit 4 r changei x bit 3 unused x bit 2 r error x bit 1 r change 0 bit 0 r run 0 the dll control status register provides information of the dll operation. used only for diagnostics. run: the dll lock status register bit (run) indicates the dll found a delay line tap in which the phase difference between the rising edge of refclk and the rising edge of sysclk is zero. after system reset, run is logic zero until the phase detector indicates an initial lock condition. when the phase detector indicates lock, run is set to logic 1. maximum time for a dll lock from reset with a stable clock should be under 12 * 256 / f(sysclk). the run register bit is cleared only by a system reset (cbi[12]) or a software reset (writing to register 2). change: the delay line tap change register bit (change) indicates the dll has moved to a new delay line tap. change is set high for eight sysclk cycles when the dll moves to a new delay line tap. error: the delay line error register bit (error) indicates the dll has run out of dynamic range. when the dll attempts to move beyond the end of the delay line, error is set high. when error is high, the dll cannot generate a dllclk phase that causes the rising edge of refclk to be aligned to the rising edge of sysclk. error is set low, when the dll captures lock again.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 152 changei: the delay line tap change event register bit (changei) indicates the change register bit has changed value. when the change register changes from a logic zero to a logic one, the changei register bit is set to logic one. the changei register bit is cleared immediately after it is read, thus acknowledging the event has been recorded. errori: the delay line error event register bit (errori) indicates the error register bit has gone high. when the error register changes from a logic zero to a logic one, the errori register bit is set to logic one. the errori register bit is cleared immediately after it is read, thus acknowledging the event has been recorded. if the errore interrupt enable is high, the int output is also asserted when errori asserts. refclki: the reference clock event register bit refclki provides a method to monitor activity on the reference clock. when the refclk primary input changes from a logic zero to a logic one, the refclki register bit is set to logic one. the refclki register bit is cleared immediately after it is read, thus acknowledging the event has been recorded. sysclki: the system clock event register bit syslcki provides a method to monitor activity on the system clock. when the sysclk primary input changes from a logic zero to a logic one, the sysclki register bit is set to logic one. the sysclki register bit is cleared immediately after it is read, thus acknowledging the event has been recorded.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 153 14 memory port mapping 14.1 context size and location the context records for s/uni-apex-1k800 are stored in 4 different areas. the majority of the context information is stored in an external ssram, the context memory. for performance reasons, some context information is stored in internal memories. there are three internal memories, the queue context, the wan port scheduler context, and the loop port scheduler context figure 29 - context location internal queue context loop class scheduler loop port threshold loop port count wan class0 wan class1 wan class2 wan class3 wan class scheduler wan port threshold wan port count up class scheduler up port threshold up port count up class0 up class1 up class2 up class3 free count overall count congestion discard max congestion id misc error external queue context memory port aperture select vc context vc statistic vc address map loop class0 loop class1 loop class2 loop class3 shape0 txslot shape1 txslot shape2 txslot shape3 txslot shape rate cell qcellstartadr address 0 qlclassstartadr qshpstartadr internal loop port scheduler context loop poll sequence loop poll weight loop class status internal wan port scheduler context wan poll weight wan class status the records for the external context memory are partitioned into four groups: vc, loop ports, shape and cells. three registers define the starting physical address of each of the loop class, shape and cell groups, with the vc group always starting at address zero. the starting address, or offset, may be of any order, and may, under certain restriction, overlap one another. for example, if the vc address map will never be enabled for a given application, then the loop class offset may be set to the
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 154 starting location of the vc address map. should the shaping not be required, then cell offset may follow immediately after the loop class records. all the port context records and all the class context records for the wan and microprocessor are located internally, and are accessed via the appropriate aperture in the context memory port. table 17 - external queue context memory map mpquadaddr context record 0..1023 vc context 16384..24575 vc statistic 24576..28671 vc address map qlclassstartadr * 1024 + {0..2047} loop class0 qlclassstartadr * 1024 + {2048..4095} loop class1 qlclassstartadr * 1024 + {4096..6143} loop class2 qlclassstartadr * 1024 + {6144..8191} loop class3 qshpstartadr * 1024 + {0..2047} shape0 txslot qshpstartadr * 1024 + {2048..4095} shape1 txslot qshpstartadr * 1024 + {4096..6143} shape2 txslot qshpstartadr * 1024 + {6144..8191} shape3 txslot qshpstartadr * 1024 + {8192..40959} shape rate qcellstartadr * 1024 + {0..65535} cell record table 18 - internal queue context memory map mpquadaddr record 0..511 loop class scheduler 512..1023 loop port threshold 1024..1535 loop port count 1536..1539 wan class0 1540..1543 wan class1 1544..1547 wan class2
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 155 mpquadaddr record 1548..1551 wan class3 1552 wan class scheduler 1553 wan port threshold 1554 wan port count up class scheduler up port threshold 1555 up port count 1556 up class0 1557 up class1 1558 up class2 1559 up class3 2048 free count 2049 overall count 2050 congestion discard 2051 maximum congestion id 2052 misc error table 19 - internal wan port scheduler context memory map mpquadaddr record 0 wan poll weight, wan class status table 20 - internal loop port scheduler context memory map mpquadaddr record 0..127 loop poll sequence 128..191 loop poll weight 192..255 loop class status writing values into unused parameter bits has no effect. however, to ensure software compatibility with future, feature-enhanced versions of the product,
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 156 unused parameter bits must be written with logic zero. reading back unused bits can produce either a logic one or a logic zero; hence, unused parameter bits should be masked off by software when read. 14.2 queue context definition many of the context parameters make references to m bit logarithmic, n bit fractional, where m is the msb of the parameter field, and n is the lsb of the parameter field. the tables below provide quick references. table 21 - 2 bit logarithmic, 2 bit fractional 2 bits fractional 0123 0 0123 1 4567 2 8101214 2 bits log 3 16 20 24 28 table 22 - 4 bit logarithmic, 2 bit fractional 2 bits fractional 0123 0 0123 1 4567 2 8101214 3 16 20 24 28 4 32 40 48 56 5 64 80 96 112 6 128 160 192 224 7 256 320 384 448 8 512 640 768 896 9 1024 1280 1536 1792 10 2048 2560 3072 3584 11 4096 5120 6144 7168 4 bits log 12 8191 table 23 - 4 bit logarithmic, 4 bit fractional 4 bits fractional 0123456789101112131415 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 16171819202122232425262728293031 4 2 32343638404244464850525456586062
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 157 3 64 68 72 76 80 84 88 92 96 100 104 108 112 116 120 124 4 128 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 5 256 272 288 304 320 336 352 368 384 400 416 432 448 464 480 496 6 512 544 576 608 640 672 704 736 768 800 832 864 896 928 960 992 7 1024 1088 1152 1216 1280 1344 1408 1472 1536 1600 1664 1728 1792 1856 1920 1984 8 2048 2176 2304 2432 2560 2688 2816 2944 3072 3200 3328 3456 3584 3712 3840 3968 9 4096 4352 4608 4864 5120 5376 5632 5888 6144 6400 6656 6912 7168 7424 7680 7936 10 8192 8704 9216 9728 10240 10752 11264 11776 12288 12800 13312 13824 14336 14848 15360 15872 11 16384 17408 18432 19456 20480 21504 22528 23552 24576 25600 26624 27648 28672 29696 30720 31744 12 32768 34816 36864 38912 40960 43008 45056 47104 49152 51200 53248 55296 57344 59392 61440 63488 13 65536 69632 73728 77824 81920 86016 90112 94208 98304 102400 106496 110592 114688 118784 122880 126976 14 131072 139264 147456 155648 163840 172032 180224 188416 196608 204800 212992 221184 229376 237568 245760 253952 15 262143 14.2.1 vc context records 14.2.1.1 vc context record mpmemselect = external queue context mpquadaddr = ici table 24 - vc context record structure mplword en (bit #) bits parameter description 33:32 unused reserved 31 vcen enables the vc. when vcen = 0, incoming cells of this vc will be discarded, cellrxerrici updated, discardcnt incremented, and the maskable interrupt qcellrxerr will be generated. any cells remaining in the queue will be transmitted, if possible. 30 vcintdis disables any maskable interrupts that this vc may generate, including qcellrxerr, qvcreaslenerr, qvcmaxthrsherr. 0 29 vcsegoam segment oam re-direct. when vcsegoam = 1, any segment oam encountered in this vc will be re- directed to the up. warning: this bit must be never be set to one if the vc is destined for the up class 0 port.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 158 mplword en (bit #) bits parameter description 28 vceeoam end to end oam re-direct. when vceeoam = 1, any end to end oam encountered in this vc will be re- directed to the up. warning: this bit must be never be set to one if the vc is destined for the up class 0 port. 27 vcvpc when vcvpc = 1, identifies this vc as vpc. when vcvpc = 0, identifies this vc as a vcc. required for oam re-direction. 26:24 vcclp0minthr sh minimum number of clp0 cells guaranteed to be allowed on a per-vc basis. values are encoded as follows: 000: 0 001: 24 010: 32 011: 48 100: 64 101: 96 110: 128 111: 256 23:18 vcmaxthrsh ppd maximum threshold for cells on a per-vc basis. 4 bits logarithmic/linear, 2 bits fractional. a zero value will effectively disable congestion at the vc level for this vc; however, the 8k-1 maximum limit still remains active. 17:12 vcclp0thrsh epd maximum threshold for clp0 cells on a per-vc basis. 4 bits logarithmic/linear, 2 bits fractional. 11:6 vcclp1thrsh epd maximum threshold for clp1 cells on a per-vc basis. 4 bits logarithmic/linear, 2 bits fractional. 5:4 vcefcimode defines efci marking. 00: no marking 01: reserved 10: mark on active clp0 thresholds 11: mark on active clp1 thresholds note: active thresholds is defined as the hierarchical maximum threshold set to a non-zero value.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 159 mplword en (bit #) bits parameter description 3:2 vcremapmod e 00: eci=ici. no vpi/vci remapping. swtag available. 01: provide an eci that is different from the ici. no vpi/vci remapping. swtag available. 10: eci=ici. vpi header remapping. swtag available. 11: eci=ici. vpi/vci header remapping. swtag not available 1 vccongmode defines congestion mode when fcq is not selected. 0: epd/ppd. congestion control is set to discard using epd/ppd. 1: congestion control operates on a cell by cell basis. when fcq is selected, this bit is reserved. warning: this bit must only be set during a vc setup. this bit must be set to 1 if the underlying traffic is not aal5. 0 vcgfrmode selects between i.363 standard definition of a frame?s clp, and the emerging gfr standard definition of a frame?s clp. zero selects the i.363 standard, a value of one selects the emerging gfr standard. this bit is reserved when cell discard congestion rules is selected. 1 33:27 vcclp0cnt[12 :6] last 7 bits of a 13-bit count of clp0 cells in both vc and class. used for congestion control for minimum resource monitoring. vc tear down and watch dog re-allocation will reduce this count by vcqclp01cnt if the vcrxbomclp = 0 and vcqueue = 1 (fcq).
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 160 mplword en (bit #) bits parameter description vcportid[11] = 0. vcportid[10:7] = must be set to 0. vc destined for a loop port. vcportid[6:0]: identifies 1 of 128 loop ports as the destination. if the loop port is configured for any-phy, all 7 bits are valid. if the loop transmit port is configured for utopia l2 master, only the first 5 bits (ports 31->0) are valid. cells received in vcs with vcportid > 31 will never be transmitted. if the loop transmit port is configured for utopia l1 master or utopia l2 slave, vcportid[6:0] must be set to 0. cells received in vcs with vcportid != 0 will never be transmitted. vcportid[11:10] = 10. vc destined for a wan ports vcportid[9:2]: reserved, must be initialized to zero. vcportid[1:0]: identifies 1 of 4 wan ports as the destination. if the wan port is configured for utopia l1 master or utopia l2 slave, vcportid[10:0] must be set to 0. cells received in vcs with vcportid != 0 will never be transmitted. 26:15 vcportid vcportid[11:10] = 11. identifies the up port as the vc?s destination vcportid[9:0]: reserved, must be initialized to zero. 14:13 vcclass assigns class to this vc destination port class is not shaped 12 vcqueue defines the queue mechanism to be used. 0: weighted fair queuing (wfq) 1: frame continuous queuing (fcq) warning: this bit must only be set during a vc setup.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 161 mplword en (bit #) bits parameter description destination port class is shaped unused reserved vcqueue = 0 (wfq), and destination port class is not shaped 11:6 vcwght class queuing weight. linear encoding, multiple of 2 with zero taking a special value of 1. (eg. 1, 2, 4, 6 ... 124, 126) warning: this bit must only be set during a vc setup. vcqueue = 1 (fcq), and destination port class is not shaped 11 vcreaspark park state bit for re-assembly watch dog. non-user cells have no effect on this bit. 10 vcreasactive indication that there is at least one cell in the queue. vc tear down and watch dog re-allocation will set this parameter to zero (empty). 9 vcreasmaxsiz e defines one of two maximum frame sizes. when this parameter is zero, frames exceeding 1366 cells will have epd invoked. when this parameter is one, frames exceeding the value programmed in the re- assembly maximum length register will have epd invoked. epds will trigger a maskable interrupt to the microprocessor. 8 vcwden marks this vc as one for the watch dog to patrol for re-assembly time outs. 7 unused reserved 6 vclenchken enables the checking of the aal5 trailer?s length field. 0: no length checking. 1: if the length field is zero, epd will be invoked. destination port class is shaped 11:6 11:6 unused reserved 5:0 vccongmode = 0 (epd/ppd congestion)
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 162 mplword en (bit #) bits parameter description 5 vctxstatus eom indication. when vctxstatus = 0, the next cell transmitted is considered the bom. used to indicate when vctxbomclp should be re-evaluated. 4 vctxbomclp state of the bom?s clp bit during transmit. used to maintain vcclp0cnt during fcq congestion and also during epd/ppd congestion when gfr mode = 1. 3:2 vcrxstatus 00: next cell queued is considered the bom. 01: next cell queued is considered a com or eom. 10: early packet discard. all cells up to and including the eom will be discarded. 11: partial packet discard. all cells but the eom will be discarded vc tear down and watch dog re-allocation will set this parameter to zero. 1 vcrxbomclp state of the bom?s clp bit during receive. used to maintain vcclp0cnt during fcq congestion and also during epd/ppd congestion when gfr mode = 1. 0 vcrxorclp vcqueue = 1 (fcq), vcgfrmode = 0, port class not shaped: this is a running or of all the clps that have been received since the bom. used by congestion control to invoke epd discard reserved in all other cases. vccongmode = 1 (cell by cell congestion) 5:0 unused reserved 33:16 vcqheadptr points to the first cell in the vc queue. a value of zero indicates that the queue is empty. vc tear down and watch dog re-allocation will set this parameter to zero. 2 15:13 vcclp0cnt[5: 3] second 3 bits of a 13-bit count of clp0 cells in both vc and class. see msb for description.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 163 mplword en (bit #) bits parameter description 12:0 vcqclp01cnt count of clp01 cells in the vc queue. used for congestion control. vc tear down and watch dog re-allocation will set this parameter to zero. 33:16 vcqtailptr points to the last cell in the vc queue 15:13 vcclp0cnt[2: 0] first 3 bits of a 13-bit count of clp0 cells in both vc and class. see msb for description. 3 12:0 vcclassqclp 01cnt count of clp01 cells in the class queue for wfq & fcq. count of clp01 cells in the class queue & txslot table combined for sfq. used for congestion control for all queuing mechanisms. note that during sfq, the maximum value this parameter can be is 1. note parameters in italics are active context information. microprocessor must mask these bits out during in-service context modification. during vc setup, these italicized parameters should be reset to zero. 14.2.1.2 vc statistics record mpmemselect = external queue context mpquadaddr = 16384 + ici/2 the statistic record for even numbered ici?s are located in long words 0 & 1. odd numbered ici?s are located in long words 2 & 3. oam cells redirected to the up are not represented by these counts. table 25 - vc statistics record structure mplword en (bit #) bits parameter description 33:32 unused reserved 0/2 31:0 vcclp0txcnt free running count of all clp0 cells that have been transmitted. 1/3 33:32 unused reserved
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 164 mplword en (bit #) bits parameter description 31:0 vcclp1txcnt free running count of all clp1 cells that have been transmitted. note parameters in italics are active context information. microprocessor must mask these bits out during in-service context modification. during vc setup, these italicized parameters should be reset to zero. 14.2.1.3 vc address map record mpmemselect = external queue context mpquadaddr = 24576 + ici/4 the address map records are packed together. ici = 0 would have the address map record located in long word 0. ici = 3 would have the address map record located in long word 3 etc. table 26 - vc address map record structure mplword en (bit #) bits parameter description 33:32 unused reserved vcremapmode = 00 31:16 swtag option to provide switch tag for the wan and loop tx interfaces. prepend of the switch tag is determined on a port by port basis. 15:0 unused reserved vcremapmode = 01 31:16 swtag option to provide switch tag for the wan and loop tx interfaces. prepend of the switch tag is determined on a port by port basis. 15:0 eci eci value that is applied to the cells upon emission, . 0/1/2/3 31:0 vcremapmode = 10
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 165 mplword en (bit #) bits parameter description 31:16 swtag option to provide switch tag for the wan and loop tx interfaces. prepend of the switch tag is determined on a port by port basis. 15:12 unused reserved 11:0 vpi vpi remap vcremapmode = 11 31:16 vci vci remap 15:12 unused reserved 11:0 vpi vpi remap 14.2.2 port context records 14.2.2.1 port threshold context record for loop ports: mpmemselect = internal queue context mpquadaddr = 512 + loop#/4 for wan ports: mpmemselect = internal queue context mpquadaddr = 1553 for microprocessor port: mpmemselect = internal queue context mpquadaddr = 1555, mplworden[1] = 1. the port context records are packed together. loop/wan = 0 would have the port context record located in long word 0. loop/wan = 3 would have the port
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 166 context record located in long word 3 etc. the microprocessor port would be located in long word 1. table 27 - port threshold context record structure mplword en (bit #) bits parameter description 33:16 unused reserved 15:8 portclp0thrs h per-port epd maximum threshold for clp0 cells that have met their minimum allocation. 4 bit logarithmic, 4 bit fractional encoding. 0/1/2/3 7:0 portclp1thrs h epd maximum threshold for clp1 cells on a per-port basis. 4 bit logarithmic, 4 bit fractional encoding. 14.2.2.2 port count context record for loop ports: mpmemselect = internal queue context mpquadaddr = 1024 + loop#/4 for wan ports: mpmemselect = internal queue context mpquadaddr = 1554 for microprocessor port: mpmemselect = internal queue context mpquadaddr = 1555, mplworden[2] = 1. the port context records are packed together. loop/wan = 0 would have the port context record located in long word 0. loop/wan = 3 would have the port context record located in long word 3 etc. the microprocessor port would be located in long word 2.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 167 table 28 - port count context record structure mplword en (bit #) bits parameter description 33:32 unused reserved 31 porten enables the port. when porten = 1, it permits cells to be received and transmitted if the class and vcs are setup. the porten should be set to zero 0 only after the class and vc have been torn down. if the porten is set to zero prior to tearing down a vc, then incoming cells will increment either the discardcnt or clpxdiscardcnt. cells that exist in the queues when the port is disabled may be transmitted. details are listed below. if porten changes from 1->0, the first cell at the head of each class queue shall be transmitted. any cells remaining in the queues will not be transmitted. exception to this case is if the port contains a shaped class, where the transmission of cells in the queues will continue until there is one cell per vc remaining. when porten = 0, all incoming cells to this port will be discarded, cellrxerrici updated, and the maskable interrupt qcellrxerr will be sent. for non fcq vcs in cell discard mode, the discardcnt is incremented when a cell is received. for non fcq vcs in epd/ppd discard mode, the discardcnt is incremented when the first cell is received, and clpxdiscardcnt is incremented when subsequent cells are received. for fcq vcs, the clpxdiscardcnt is incremented when a cell is received. if a frame is in the process of being re-assembled when porten = 1->0, the clpxdiscardcnt will be incremented by the length of the re-assembly queue plus 1 (cell that arrived). 30:28 unused reserved 0/1/2/3 27:20 portmaxthrsh maximum threshold for cells on a per-port basis. 4 bit logarithmic, 4 bit fractional encoding. a zero value will effectively disable congestion at the port level for this port.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 168 mplword en (bit #) bits parameter description 19:18 unused reserved 17:0 portcnt total count of all cells queued for this port. used for congestion control. vc tear down and watch dog re-allocation will reduce this count by vcqclp01cnt. class tear down will reduce this count by classcnt. note parameters in italics are active context information. microprocessor must mask these bits out during in-service context modification. during port setup, these italicized parameters should be reset to zero.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 169 14.2.3 class context records 14.2.3.1 class scheduler context record for loop ports: mpmemselect = internal queue context mpquadaddr = loop#/4 for wan ports: mpmemselect = internal queue context mpquadaddr = 1552 for microprocessor port: mpmemselect = internal queue context mpquadaddr = 1555, mplworden[0] = 1. the port context records are packed together. loop/wan = 0 would have the port context record located in long word 0. loop/wan = 3 would have the port context record located in long word 3 etc. the microprocessor port would be located in long word 0. table 29 - class scheduler record structure mplword en (bit #) bits parameter description 33:32 unused reserved classfragen = 0 0/1/2/3 31:20 31:28 class1celllmt number of cells that can be transmitted from another class while class1 is waiting for a transmission opportunity before class1 enters the starvation condition. 2 bit logarithmic, 2 bit fractional encoding. when classpacket = 1, this parameter should be set to 0 to force strict priority.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 170 mplword en (bit #) bits parameter description 27:24 class2celllmt number of cells that can be transmitted from another class while class2 is waiting for a transmission opportunity before class2 enters the starvation condition. 2 bit logarithmic, 2 bit fractional encoding. when classpacket = 1, this parameter should be set to 0 to force strict priority. 23:20 class3celllmt number of cells that can be transmitted from another class while class3 is waiting for a transmission opportunity before class3 enters the starvation condition. 2 bit logarithmic, 2 bit fractional encoding. when classpacket = 1, this parameter should be set to 0 to force strict priority. classfragen = 1 31 unused reserved 30:20 classcelllmt maximum number of cells that can be transmitted from a class before the class scheduler selects another class to transmit from. a value of zero is functionally equivalent to a value of one. 19 classfragen enable packet fragmentation class scheduling. 18 classpacket places the class scheduler into a packet or frame continuous mode. in packet mode, if a vc set to fcq is at the head of the class queue, the class scheduler will send out the entire packet prior to servicing a different class. when set, classncelllmt must be set to zero to ensure strict priority scheduling. warning: this bit must only be set during a class setup. this must be set to 1 when classfragen = 1. classpacket = 0 unused reserved classpacket = 1 17:15 17 classstatus when classstatus = 0, indicates that the next cell transmitted is considered the bom of a packet.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 171 mplword en (bit #) bits parameter description 16:15 classserviced indicates the class that is currently being serviced. classfragen = 0 14:10 class1cellcnt current number of cells that have been transmitted while class1 has remained unserviced. 9:5 class2cellcnt current number of cells that have been transmitted while class2 has remained unserviced. 4:0 class3cellcnt current number of cells that have been transmitted while class3 has remained unserviced. classfragen = 1 14:11 unused reserved 14:0 10:0 classcellcnt current number of cells that have been transmitted from the class indicated by classserviced. note parameters in italics are active context information. microprocessor must mask these bits out during in-service context modification. during class setup, these italicized parameters should be reset to zero. 14.2.3.2 class 0 through 3 context record for loop ports: mpmemselect = external queue context mpquadaddr = qlclassstartadr * 1024 + class * 2048 + loop# for wan ports: mpmemselect = internal queue context mpquadaddr = 1536 + class * 4 + wan#, class = 0,1,2,3 for microprocessor ports: mpmemselect = internal queue context
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 172 mpquadaddr = 1556 + class * 4, class = 0,1,2,3 table 30 - class context record structure mplword en (bit #) bits parameter description 33:32 unused reserved 31 classen enable the class queue. when classen = 1, it permits cells to be received and transmitted if the port and vcs are setup. the classen should be set to zero 0 only after the vc has been torn down. if the classen is set to zero prior to tearing down a vc, then incoming cells will increment either the discardcnt or clpxdiscardcnt. details are listed below. when classen = 0, all incoming cells to this class will be discarded, cellrxerrici updated, and the maskable interrupt qcellrxerr will be sent. for non fcq vcs, any cells remaining in the queue will be transmitted, if possible. if the vc is in cell discard mode, cells received will cause the discardcnt to increment. if the vc is in epd/ppd discard mode, the discardcnt is incremented when the first cell is received, and clpxdiscardcnt is incremented when subsequent cells are received. for fcq vcs, the clpxdiscardcnt is incremented when a cell is received. if a frame is in the process of being re-assembled when classen = 1->0, the clpxdiscardcnt will be incremented by the length of the re-assembly queue plus 1 (cell that arrived). 30:24 unused reserved 23:16 classmaxthrs h maximum threshold for cells on a per-class basis. 4 bit logarithmic, 4 bit fractional encoding. a zero value will effectively disable congestion at the class level for this class. 0 15:8 classclp0thr sh per- class epd threshold for clp0 cells that have met their minimum buffer allocation. 4 bit logarithmic, 4 bit fractional encoding.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 173 mplword en (bit #) bits parameter description 7:0 classclp1thr sh epd maximum threshold for clp1 cells on a per- class basis. 4 bit logarithmic, 4 bit fractional encoding. 33:26 unused reserved 25:20 classcnt[17:1 2] last 6 bits of an 18 bit count of all cells in both class, txslot (sfq only) & vc queue. used for congestion control. vc tear down and watch dog re-allocation will reduce this count by vcqclp01cnt class tear down will set this parameters to zero. 19:18 unused reserved 1 17:0 classheadptr points to first cell in linked list of cell records for class queue. a value of zero indicates that the queue is empty; however, during shaping or vcmerge, it does not indicate that the class is empty. class tear down will set this parameters to zero. 33:32 unused reserved 31:20 classcnt[11:0] first 12 bits of an 18 bit count of all cells in both class & vc queue. see msb for description. 19:18 unused reserved 2 17:0 classtailptr points to last cell in linked list of cell records for class queue. class tear down will set this parameters to zero. 3 33:0 unused reserved note parameters in italics are active context information. microprocessor must mask these bits out during in-service context modification. during class setup, these italicized parameters should be reset to zero.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 174 14.2.4 shaping context records 14.2.4.1 shape txslot context record mpmemselect = external queue context mpquadaddr = qshpstartadr * 1024 + shape# * 2048 + txslot/2, txslot = 0..4095 the txslot record for even numbered txslots are located in long words 0 & 1. odd numbered txslots are located in long words 2 & 3. table 31 - shape txslot context record structure mplword en (bit #) bits parameter description 33:16 shptxqheadp tr head pointer for the traffic shaped transmission queue. a value of zero indicates that the queue is empty. 0/2 15:0 unused reserved 33:16 shptxqtailptr tail pointer for the traffic shaped transmission queue. 1/3 15:0 shptxqcnt number of cells en-queued on this time slot. note parameters in italics are active context information. microprocessor must mask these bits out during in-service context modification. during vc setup, these italicized parameters should be reset to zero. 14.2.4.2 shape rate context record mpmemselect = external queue context mpquadaddr = qshpstartadr * 1024 + 8192 + ici/2 the shape rate record for even numbered ici?s are located in long words 0 & 1. odd numbered ici?s are located in long words 2 & 3.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 175 table 32 - shape rate context record structure mplword en (bit #) bits parameter description 33:32 unused reserved 31:28 shplatebits number of bits used to represent shptxslotslate, the ?late counter?. in unit of timeslots, mbs = 2 ^ shplatebits. 27:16 shpcdvt cell delay variance tolerance for the connection. format is in integer number of timeslots. it must be less than shpincr, and shpcdvt < 2 ^ shplatebits. relative to the atmf 4.1 specification terminology, this value is equivalent to t ? ts, where t = 1/pcr, ts = 1/scr. this parameter must be set to zero if shpprescale = 0. 15:13 unused reserved 12 shpprescale determines the resolution of the incr field 0/2 11:0 shpincr increment field for scr-gcra. . format is in integer number of timeslots if prescale = 1 or in integer + 1/64 fractional timeslots xxxxxx.xxxxxx (6 bit integer part w/ 6-bit fractional part) if shpprescale = 0. the shpincr must always be greater than or equal to 1.0. 33:30 unused reserved 29:18 shptxslotslat e indicates the accumulated number of late time slots that the previous cells for this connection were output. shplatebits specifies the number of least significant bits used to represent this value. 17:12 shprem indicates the remainder when scheduling at fractional timeslots. 1/3 11:0 shptxslot indicates the last time slot that this connection was scheduled
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 176 note parameters in italics are active context information. microprocessor must mask these bits out during in-service context modification. during vc setup, these italicized parameters should be reset to zero. 14.2.5 cell context record mpmemselect = external queue context mpquadaddr = qcellstartadr * 1024 + cellptr/4 the cell records are packed together. cellptr = 0 would have the cell record located in long word 0. cellptr = 3 would have the cell record located in long word 3 etc. table 33 - cell context record structure mplword en (bit #) bits parameter description 33:16 cellnextptr points to the next cell in the linked list 0/1/2/3 15:0 cellici vc identifier note parameters in italics are active context information. microprocessor must mask these bits out during in-service context modification. during freelist setup, cellici should be reset to zero. 14.2.6 misc context note: 1) masked writes are not permitted for any of the misc. context records. 2) parameters in italics are active context information. during chip setup, these italicized parameters should be reset to zero unless otherwise stated. mpmemselect = internal queue context mpquadaddr = 2048
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 177 table 34 - free count context structure mplword en (bit #) bits parameter description 33:18 unused reserved 0 17:0 freecnt total count of all cells available for buffering. this parameter must be initialized to the cell buffer size minus 1. vc tear down and watch dog re-allocation will increase this count by vcqclp01cnt. class tear down will increase this count by classcnt. 33:18 unused reserved 1 17:0 freeheadptr points to the first cell context record of the linked list that holds all the cell records that are free for cell buffering. 33:18 unused reserved 2 17:0 freetailptr points to the last cell context record of the linked list that holds all the cell records that are free for cell buffering. 3 33:0 unused reserved mpquadaddr = 2049 table 35 - overall count context structure mplword en (bit #) bits parameter description 33:18 unused reserved 0 17:0 loopcnt total count of all cells queued for all loop ports. this is the ?dircnt? for cells destined to a loop port. vc tear down and watch dog re-allocation will reduce this count by vcqclp01cnt if vc is destined for the loop. class tear down will reduce this count by classcnt if class is destined for the loop. 1 33:18 unused reserved
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 178 mplword en (bit #) bits parameter description 17:0 wancnt total count of all cells queued for all wan ports. this is the ?dircnt? for cells destined to a wan port. vc tear down and watch dog re-allocation will reduce this count by vcqclp01cnt if vc is destined for the wan. class tear down will reduce this count by classcnt if class is destined for the wan. 2 33:0 unused reserved 3 33:0 unused reserved mpquadaddr = 2050 table 36 - congestion discard context structure mplword en (bit #) bits parameter description 33:32 unused reserved 0 31:0 clp0discardc nt free running count of all inbound clp0 cells that have been discarded due to congestion , re-assembly maximum length limit, disabled class/port, or zero length check. 33:16 unused reserved 1 15:0 clp0discardi ci these bits contain the ici of the last time a clp0 cell was discarded due to congestion. 33:32 unused reserved 2 31:0 clp1discardc nt free running count of all inbound clp1 cells that have been discarded due to congestion, re-assembly maximum length limit, disabled class/port, or zero length check. 33:0 unused reserved 3 15:0 clp1discardi ci these bits contain the ici of the last time a clp1 cell was discarded due to congestion. mpquadaddr = 2051
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 179 table 37 - maximum congestion id context structure mplword en (bit #) bits parameter description 33:16 unused reserved 0 15:0 vcmaxthrsher rici these bits contain the ici of the last vc queue that has reached the congestion limit of vcmaxthrsh. 33:14 unused reserved 13:12 classmaxthrs herrid these bits identify which class of the last class queue that has reached the classmaxthrsh limit. 1 11:0 classmaxthrs herrportid these bits contain the port id of the last class queue that has reached the classmaxthrsh limit. see vc context record for portid encoding. 33:12 unused reserved 2 11:0 portmaxthrsh errportid these bits contain the port id of the last port queue that has reached the portmaxthrsh limit. see vc context record for portid encoding. 3 33:0 unused reserved mpquadaddr = 2052 table 38 - misc error context structure mplword en (bit #) bits parameter description 33:32 unused reserved 0 31:0 discardcnt free running general discard count of all the cells that have been discarded due to reasons other than congestion. possible causes include re-assembly time out, cell encountered on a disable vc/class/port, tear down of a vc or class queue.. 33:16 unused reserved 1 15:0 cellrxerrici these bits contain the ici of the last cell that was destined for a vc that was not enabled. this could be caused when any of the following enables are not set to 1: vcen, classen, porten. 2 33:16 unused reserved
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 180 mplword en (bit #) bits parameter description 15:0 vcreaslenerr ici these bits contain the ici of the last vc that violated the maximum permitted re-assembly length. 33:16 unused reserved 3 15:0 vcreastimee rrici these bits contain the ici of the last timed out vc discovered by the watch dog. 14.3 wan port scheduler context 14.3.1 wan transmit port polling weight record mpmemselect = wan port scheduler internal context mpquadaddr = 0 the wan transmit port polling weight records are packed together note: only single long word accesses are permitted at any one time. table 39 - wan transmit port polling weight mplword en (bit #) bits parameter description 31:14 unused reserved 13:12 wanpollwght 3 wan polling weight for port 3 11:10 unused reserved 9:8 wanpollwght 2 wan polling weight for port 2 7:6 unused reserved 5:4 wanpollwght 1 wan polling weight for port 1 3:2 unused reserved 0 1:0 wanpollwght 0 wan polling weight for port 0
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 181 the polling weight determines how frequently the wan port scheduler will evaluate whether the corresponding wan port should be polled for transmit packet available. the weights are logarithmic. the weight determines how many of the total polling cycles a port participates in. a weight should be set according to the following table: table 40 - wan poll weight format wanpollwght[1:0] weight ratio 00 1 01 1/2 10 1/4 11 1/8 14.3.2 wan transmit class status record mpmemselect = wan port scheduler internal context mpquadaddr = 0 note: only single long word accesses are permitted at any one time. table 41 - wan class status mplword en (bit #) bits parameter description 31:16 unused reserved 15:12 wanclassstat 3 wan class status for port 3 11:8 wanclassstat 2 wan class status for port 2 7:4 wanclassstat 1 wan class status for port 1 1 3:0 wanclassstat 0 wan class status for port 0 the bits in each wan class status indicates whether a cell destined for the given wan is currently in the queue waiting for transmission. bit 0 represents class 0, bit 1 represents class 1 etc.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 182 warning : masking should always be applied over active classes during writes. 14.4 loop port scheduler context 14.4.1 loop transmit port polling sequence record mpmemselect = loop port scheduler internal context mpquadaddr = loop#/16 the loop transmit port polling sequence records are packed. each long word contains sequence numbers for four ports. each quad word contains entries for 16 ports. there are a total of 8 quad words in the table for a total of 128 loop ports. long word 0 contains weight for ports 0-3, long word 1 contains weight for ports 4-7 etc. note: only single long word accesses are permitted at any one time. table 42 - loop transmit port polling sequence mplword en (bit #) bits parameter description 31 unused reserved 30:24 looppollseq3 loop polling sequence for port ((mplworden bit *4) + 3) 23 unused reserved 22:16 looppollseq2 loop polling sequence for port ((mplworden bit *4) + 2) 15 unused reserved 15:8 looppollseq1 loop polling sequence for port ((mplworden bit *4) + 1) 7 unused reserved 0/1/2/3 6:0 looppollseq0 loop polling sequence for port ((mplworden bit *4) + 0) the polling sequence determines when within a loop port scheduler weight polling cycle this port will be evaluated to be polled. this allows software to evenly distribute the polling of ports of the same weight. the loop port scheduler will compare the n lsb?s of the looppollseq with the current scheduler poll sequence to decide if that port should be polled (n is equal to the port?s
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 183 looppollwght). when these 2 values match and that port has transmit data to be sent, that port is scheduled to be polled. 14.4.2 loop transmit port polling weight record mpmemselect = loop port scheduler internal context mpquadaddr = 128 + loop#/32 the loop transmit port polling weight records are packed together. each long word contains weights for 8 loop ports. there are a total of 4 quad words in the table for a total of 128 loop ports. long word 0 contains weight for ports 0-7, long word 1 contains weight for ports 8-15 etc. note: only single long word accesses are permitted at any one time. table 43 - loop transmit port polling weight mplword en (bit #) bits parameter description 31 unused reserved 30:28 looppollwght 7 loop polling weight for port ((mplworden bit *8) + 7) 27 unused reserved 26:24 looppollwght 6 loop polling weight for port ((mplworden bit *8) + 6) 23 unused reserved 22:20 looppollwght 5 loop polling weight for port ((mplworden bit *8) + 5) 19 unused reserved 18:16 looppollwght 4 loop polling weight for port ((mplworden bit *8) + 4) 15 unused reserved 14:12 looppollwght 3 loop polling weight for port ((mplworden bit *8) + 3) 11 unused reserved 0/1/2/3 10:8 looppollwght 2 loop polling weight for port ((mplworden bit *8) + 2)
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 184 mplword en (bit #) bits parameter description 7 unused reserved 6:4 looppollwght 1 loop polling weight for port ((mplworden bit *8) + 1) 3 unused reserved 2:0 looppollwght 0 loop polling weight for port ((mplworden bit *8) + 0) the polling weight determines how frequently the loop port scheduler will evaluate whether the corresponding loop port should be polled for transmit packet available. 14.4.3 loop transmit class status record mpmemselect = loop port scheduler internal context mpquadaddr = 192 + loop#/32 the loop class status records are packed together. each long word contains status for 8 loop ports. there are a total of 4 quad words in the table for a total of 128 loop ports. long word 0 contains weight for ports 0-7, long word 1 contains weight for ports 8-15 etc. note: only single long word accesses are permitted at any one time. table 44 - loop class status mplword en (bit #) bits parameter description 31:28 loopclassstat 7 loop class status for port ((mplworden bit *8) + 7) 27:24 loopclassstat 6 loop class status for port ((mplworden bit *8) + 6) 23:20 loopclassstat 5 loop class status for port ((mplworden bit *8) + 5) 0/1/2/3 19:16 loopclassstat 4 loop class status for port ((mplworden bit *8) + 4)
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 185 mplword en (bit #) bits parameter description 15:12 loopclassstat 3 loop class status for port ((mplworden bit *8) + 3) 11:8 loopclassstat 2 loop class status for port ((mplworden bit *8) + 2) 7:4 loopclassstat 1 loop class status for port ((mplworden bit *8) +1) 3:0 loopclassstat 0 loop class status for port ((mplworden bit *8) + 0) the bits in each loop class status indicates whether a cell destined for the given loop is currently in the queue waiting for transmission. bit 0 represents class 0, bit 1 represents class 1 etc. warning : masking should always be applied over active classes during writes.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 186 15 test features description 15.1 jtag test port the s/uni-apex-1k800 jtag test access port (tap) allows access to the tap controller and the 4 tap registers: instruction, bypass, device identification and boundary scan. using the tap, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. table 45 - instruction register length - 3 bits instructions selected register instruction codes, ir[2:0] extest boundary scan 000 idcode identification 001 sample boundary scan 010 bypass bypass 011 bypass bypass 100 stctest boundary scan 101 bypass bypass 110 bypass bypass 111 table 46 - identification register length 32 bits version number 0h part number 7326h manufacturer's identification code 0cdh device identification 073260cdh table 47 - boundary scan register please see file ?s/uni-apex-1k800 jtag scan register.xls?
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 187 boundary scan cells in the following diagrams, clock-dr is equal to tck when the current controller state is shift-dr or capture-dr, and unchanging otherwise. the multiplexer in the centre of the diagram selects one of four inputs, depending on the status of select lines g1 and g2. the id code bit is as listed in the boundary scan register table located above. figure 30 - input observation cell (in_cell) input pad d c clock-dr scan chain out input to internal logic shift-dr scan chain in 1 2 mux 1 2 1 2 1 2 i.d. code bit idcode g1 g2
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 188 figure 31 - output cell (out_cell) extest d c d c g1 g2 12 mux g1 1 1 mux output or enable from system logic scan chain in scan chain out output or enable shift-dr clock-dr update-dr 12 12 12 idoode i.d. code bit figure 32 - bi-directional cell (io_cell) d c d c g1 1 1 mux output from internal logic scan chain in scan chain out extest output to pin shift-dr clock-dr update-dr input from pin input to internal logic g1 1 2 mux 1 2 1 2 1 2 g2 idcode i.d. code bit
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 189 figure 33 - layout of output enable and bidirectional cells output enable from internal logic (0 = drive) input to internal logic output from internal logic scan chain in scan chain out i/o pad out_cell io_cell
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 190 16 operation please refer to the document ?s/uni-apex h/w programmer?s guide?, pmc- 991454
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 191 17 functional timing 17.1 microprocessor interface the following diagrams illustrate the various handshaking required for microprocessor reads and writes. figure 34 shows a single read and write operation with bus polarity set to 1. on the first cycle, burstb is sampled inactive; therefore, it is expected that the cycle be a single data transfer, and the blast signal is of no significance. the subsequent 2 cycles have burstb sampled active hence the transfer cycle is terminated when both blast and readyb are asserted. note that between each transfer, there is a turn around cycle provided by the external interface to ensure that there is no bus contention on back to back transfers on the ad bus. figure 34 - single word read and write 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 a d a d a d read, 4 wait cycles read, 4 wait cycles write, 1 wait cycle write, 1 wait cycle read, 3 wait cycles read, 3 wait cycles bclk buspol csb adsb ad(31:0) wr burstb blast readyb btermb figure 35 shows a burst read and write operation with bus polarity set to 0. the first and third access illustrate transfers that are terminated by the s/uni-apex- 1k800 via the assertion of btermb. the second and fourth access illustrate transfers that are terminated by the external interface via the assertion of blast. note that between each transfer, there is no turn around cycle. care must be taken to examine the ac timing to ensure that there is no bus contention on the ad bus between a read followed by a write transfer.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 192 figure 35 - burst read and write 1 2 3 45 6 7 8 91011121314151617181920212223242526272829303132 a d a d a d a d d burst write, 1 wait cycles, bt e burst write, 1 wait cycles, bt e burst read, 4 wait cycles, no btermb burst read, 4 wait cycles, no btermb burst read, 3 wait cycles, btermb issued burst read, 3 wait cycles, btermb issued bclk buspol csb adsb ad(31:0) wr burstb blast readyb btermb figure 36 shows consecutive write operations using the wrdoneb signal without the readyb. write operations may only begin when wrdoneb is sampled low by the external interface. on the first data transfer, the cycle is terminated normally. subsequent access does not begin until wrdoneb is sampled low by the external interface. this interface is used when the external processor is incapable of dealing with wait states during write operations.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 193 figure 36 - consecutive write accesses using wrdoneb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a d0 a d 0 d 1 d 2 d 3 bclk buspol csb adsb ad(31:0) wr burstb blast wrdoneb 17.2 sdram interface the following three diagrams depict the timing for signals destined for the pins of the sdram during the activate-read (with auto-precharge), activate-write (with auto-precharge), and auto-refresh command sequences. the cbcmd signal is not an actual signal; it merely represents the memory access command formed by the combination of the individual sdram control signals (cbcsb_o, cbrasb_o, etc.). another note is that reads/writes are always done in bursts of eight words; the first involves the even banks and the second burst involves the odd banks in sdram.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 194 figure 37 - read timing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 act 0 desel/nop rd0 desel/nop act1 desel/nop rd1 desel/nop even bank odd bank 00 even row even col odd row odd col even row prea odd row prea d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 trcd trcd sysclk cbcmd cbcsb cbrasb cbcasb cbweb cbdqm[1:0] cbbs[1:0] cba[11, 9:0] cba[10] cbdq[31:0] figure 38 - write timing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 act0 desel/nop wr0 desel/nop act1 desel/nop wr1 desel/nop even bank odd bank 00 even row even col odd row odd col even row prea odd row prea d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 trcd trcd sysclk cbcmd cbcsb cbrasb cbcasb cbweb cbdqm[1:0] cbbs[1:0] cba[11, 9:0] cba[10] cbdq[31:0]
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 195 figure 39 - refresh 1 2 3 4 5 6 7 8 9 10 11 12 refa desel/nop act desel/nop 00 400h trc sysclk cbcmd cbcsb cbrasb cbcasb cbweb cbdqm[1:0] cbbs[1:0] cba[11:0] cbdq[31:0] figure 40 - power up and initialization sequence 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 no p pre a no p ref a no p ref a no p mr s 00 400h 033h trc (9cyc) trp (3cyc) sdram initialization sequence (78 cyc) refa & trc (9 cyc) sequence must be repeated 8 times, prior to mrs cbri performs first arbitration on cycle following mrs sysclk vcc bucb_cben cbcmd cbcsb cbrasb cbcasb cbweb cbdqm[1:0] cbbs[1:0] cba[11:0] cbdq[31:0] 17.3 zbt ssram interface the following diagram depicts the timing for signals destined for the pins of the pipelined zbt ssram during a read followed by a write cycle. the cmcmd
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 196 signal is not an actual signal; it merely represents the memory access command formed by the combination of the individual ssram control. figure 41 - read followed by write timing 1 2 3 4 5 6 7 8 9 rd desel w r desel a1 a2 a1 a2 r1 w2 r1 w2 sysclk cmcmd cmceb cmrwb cma[18:0] cmab[18:17] cmd[33:0] cmp[1:0] 17.4 late write ssram interface the following diagram depicts the timing for signals destined for the pins of the register to register late write ssram during a read followed by a write cycle. the cmcmd signal is not an actual signal; it merely represents the memory access command formed by the combination of the individual ssram control.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 197 figure 42 - read followed by write timing 1 2 3 4 5 6 7 8 9 rd desel w r desel a1 a2 a1 a2 r1 w2 r1 w2 1cyc 2cyc sysclk cmcmd cmceb cmrwb cma[18:0] m ab[18:17] cmd[33:0] cmp[1:0] 17.5 any-phy/utopia interfaces while the following diagrams present representative waveforms, they are not an attempt to unambiguously describe the interfaces. the pin description section is intended to present the detailed pin behavior and constraints on use. the following parameters apply to all any-phy/utopia interface figures: n = 2 for wan, 5 for loop m = 7 for 8 bit mode, 15 for 16 bit mode k = function of 8/16 bit mode, and number of prepends selected. 17.5.1 receive master/transmit slave interfaces figure 43 gives an example of the functional timing of the receive interface when configured as a utopia level 2 compliant transmit slave. the interface responds to the polling of address ?apex? (which matches the address defined by the register {loop/wan}rxslaveaddr[n:0]) by asserting rpa when it is capable of accepting a complete cell. as a result, the master selects the s/uni- apex-1k800 by presenting ?apex? again during the last cycle renb is high. had not the device been selected, rsop, rdat[n:0] and rprty would have remained high-impedance.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 198 figure 43 illustrates that a cell transfer may be paused by deasserting renb. the device is reselected by presenting address ?apex? the last cycle renb is high to resume the transfer. figure 43 - utopia l2 transmit slave (loop & wan) 1 rclk apex dev 2 data k data k-2 data k-1 data 0 data 1 apex data 2 rclk radr [n:0] rpa rdat[m:0], rprty renb rsop figure 44 gives an example of the functional timing of the receive interface when configured as a utopia level 1 compliant receive master. when s/uni-apex- 1k800 is capable of accepting at least one more cell, and it samples rpa high, a transfer cycle is initiated. if the s/uni-apex-1k800 is capable of receiving an additional cell and rpa is sampled high, it will de-assert renb first before initiating the next transfer. once transfer is initiated, renb will remain asserted until the last data is received. figure 44 - utopia l1 receive master (loop & wan) data 0 data k data 1 data k-1 rclk radr [n:0] rpa rdat[m:0], rprty renb rsop
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 199 figure 45 gives an example of the functional timing of the receive interface when configured as a utopia level 2 compliant receive master. when s/uni-apex- 1k800 is capable of accepting at least one more cell, the interface polls addresses until it receives an asserted rpa. as a result, the master re-selects the same radr again during the last cycle renb is high to initiate a transfer. if the s/uni-apex-1k800 is capable of receiving an additional cell, it will continue to poll for the next available port. once transfer is initiated, renb will remain asserted until the last data is received. figure 45 - utopia l2 receive master (loop & wan) 1 rclk dev 0 dev n data k data k-1 data 0 data 1 data 2 dev 0 dev x dev n data 0 rclk radr [n:0] rpa rdat [m:0], rprty renb rsop figure 46 gives an example of the functional timing of the receive interface when configured as a any-phy compliant receive master. when s/uni-apex-1k800 is capable of accepting at least one more cell, the interface polls addresses until it receives an asserted rpa. as a result, the master re-selects the same radr again during the last cycle renb is high to initiate a transfer. if the s/uni-apex- 1k800 is capable of receiving an additional cell, it will continue to poll for the next available port. once transfer is initiated, renb will remain asserted until the last data is received.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 200 figure 46 - any-phy receive master (loop & wan) dev 0 dev x dev n 2 rclk dev 0 dev n dev 0 adr pre data k data 1 data k-1 d rclk radr [n:0] rpa rdat [m:0], rprty renb rsx rsop 17.5.2 transmit master/receive slave interfaces figure 47 gives an example of the functional timing of the transmit interface when configured as a utopia level 2 compliant receive slave. the interface responds to the polling of address ?apex? (which matches the address defined by the register {loop/wan}txslaveaddr[n:0]) by asserting tpa when it is capable of transmitting a complete cell. as a result, the master selects the s/uni-apex by presenting ?apex? again during the last cycle tenb is high. had not the device been selected, tsop, tdat[n:0] and tprty would have remained high-impedance. figure 47 illustrates that a cell transfer may be paused by deasserting tenb. the device is reselected by presenting address ?apex? the last cycle tenb is high to resume the transfer.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 201 figure 47 - utopia l2 receive slave (loop & wan) 1 tclk apex dev 2 data k-3 data k data k-2 data k-1 data 0 data 1 apex tclk tadr [n:0] tpa tdat[m:0], tprty tenb tsop figure 48 gives an example of the functional timing of the wan transmit interface when configured as a utopia l1 compliant transmit master. the address presented on the wtadr bus comes from the wantxslaveaddr register. when the s/uni-apex-1k800 samples wtpa as high and there is a complete cell is available for transfer, a transfer is initiated. if wtpa remains high at the end of the first transfer, and if a cell is available for transfer, another transfer is initiated. transfers complete without pausing. figure 48 - wan utopia l1 transmit master data 0 data k data 1 data 0 data 1 register wantxslaveaddr wtclk wtadr [2:0] wtpa wtdat[m:0], wtprty wtenb tsop figure 49 gives an example of the functional timing of the loop transmit interface when configured as a utopia l1 compliant transmit master. it is nearly identical to the wan utopia l1 transmit master, with the exception that the address on the ltadr bus is indeterminate and should not be used.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 202 figure 49 - loop utopia l1 transmit master data 0 data 1 data k data 2 data k-1 data 0 ltclk ltadr [11:0] ltpa ltdat [m:0], ltprty ltenb ltsop figure 50 gives an example of the functional timing of the wan transmit interface when configured as a utopia l2 compliant transmit master. the s/uni-apex-1k800 polls ports that it has a complete cell available for transfer. the receiving device responds by driving wtpa. when the first port asserts wtpa, the s/uni-apex-1k800 will stop polling, and drives wtadr with the port?s address until the transfer is initiated. once the transfer is initiated, as indicated by the assertion of wtenb, polling recommences and continues until the next port asserts wtpa. if the port in transfer is polled at the same time, wtpa is considered valid only for the last 4 clocks from the end of the transfer. the second transfer will not begin until the first transfer is complete. transfers complete without pausing. figure 50 - wan utopia l2 transmit master 1 tclk dev x dev x dev 0, data 0 data k data 1 dev n, data 0 data 1 data 2 dev 0 dev n dev n data 2 dev 0 wtclk wtadr [2:0] wtpa wtdat[m:0], wtprty wtenb wtsop figure 51 gives an example of the functional timing of the loop transmit interface when configured as a utopia l2 compliant transmit master. it is nearly identical to the wan utopia l2 transmit master, with the exception of the polling
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 203 behaviour. unlike the wan, the loop interface will assert a null address once a ltpa is sampled high. the null address remains on the ltadr bus until the port selection marking the start of the next transfer. transfers complete without pausing. figure 51 - loop utopia l2 transmit master 1 tclk phy 0 phy 0 phy 1 phy 1 dev 0,data 1 data 2 data k data k-1 dev 1, data 1 phy x phy x phy 1 phy 1 ltclk ltadr [5:0] ltpa ltdat [m:0], ltprty ltenb tsop figure 52 gives an example of the functional timing of the wan transmit interface when configured as a any-phy compliant transmit master. the s/uni- apex-1k800 polls ports that it has a complete cell available for transfer. the receiving device responds by driving wtpa. when the first port asserts wtpa, the s/uni-apex-1k800 will stop polling, and drives wtadr with the port?s address until the transfer is initiated. once the transfer is initiated, as indicated by the assertion of wtenb & wtsx, polling recommences and continues until the next port asserts wtpa. transfers complete without pausing. figure 52 - wan any-phy transmit master 2 tclk data 0 data k data 1 data 0 adr pre, dev 1 adr pre, dev 0 dev 0 dev x dev 0 dev 1 dev 1 wtclk wtadr [2:0] wtpa wtdat[m:0], wtprty wtenb wtsx tsop
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 204 figure 53 gives an example of the functional timing of the loop transmit interface when configured as a any-phy compliant transmit master. the s/uni-apex- 1k800 polls ports that it has a complete cell available for transfer. the receiving device responds by driving ltpa. positive responses are recorded, and will eventually result in a data transfer. polling continues independent of the data transfer state. data transfers are initiated with the assertion of ltenb & ltsx, and complete without pausing. figure 53 - loop any-phy transmit master 2 tclk phy 0 phy 1 phy 0 phy 1 phy 0 adr pre, phy 8 data 1 data 2 data k data 3 data k-1 data 1 adrpre, phy2 phy 7 ltclk ltadr [7:0] ltpa t dat [m:0], ltprty ltenb ltsx ltsop
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 205 18 absolute maximum ratings maximum rating are the worst case limits that the device can withstand without sustaining permanent damage. they are not indicative of normal mode operation conditions. table 48 - absolute maximum ratings parameter symbol value storage temperature t st -40c to +125c supply voltage v dd -0.3v to +4.6v voltage on any pin v in 0v to v ddo +0.5v static discharge voltage 1000 v latch-up current 100 ma dc input current i in 10 ma lead temperature +230c junction temperature t j +150c
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 206 19 d.c. characteristics t a = -40c to +85c, v vdd = 3.3 v 0.3v, v pch = 2.5 v 8% (typical conditions: t a = 25c, v vdd = 3.3 v, v pch = 2.5 v ) table 49 - d.c. characteristics symbol parameter min typ max unit s conditions vdd pin power supply 3.0 3.3 3.6 volts pch core power supply 2.3 2.5 2.7 volts vil input low voltage -0.3 1.4 0.8 volts vih input high voltage 2.0 1.4 5.5v volts vol output or bidirectional low voltage 0.4 volts vdd = min, iol = 2 ma, vi = vil voh output or bidirectional high voltage 2.4 volts vdd = min, ioh = -2 ma, vi = vih vt+ schmitt input high threshold voltage 1.39 1.82 2.06 volts for pins rstb & trstb vt- schmitt input low threshold voltage 0.8 1.24 1.46 volts for pins rstb & trstb vth schmitt input hysteresis voltage 0.51 volts for pins rstb & trstb iilpu input low leak current +10 +100 a vil = gnd. notes 1, 3 iihpu input high leak current -10 +10 a vih = vddo. notes 1, 3 iil input low leak current -10 +10 a vil = gnd. notes 2, 3
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 207 symbol parameter min typ max unit s conditions iih input high current -10 +10 a vih = vddo. notes 2, 3 cin input capacitance 6 pf excluding package, package typically 1 pf cout output capacitance 6 pf excluding package, package typically 1 pf cio bidirectional capacitance 6 pf excluding package, package typically 1 pf iddop operating current 513 (core) 99 (i/o unload ed) 410 (i/o loaded ) ma t a = 85 degc vdd = vdd (max),, pch = pch (max) sysclk = 80mhz, bclk = 66mhz wrclk, wtclk, lrclk, ltclk = 52mhz, all any-phy i/f in master modes 1.66mcells/s aggregate throughput i/o loaded: 80pf on loop any-phy i/f 40pf on wan any-phy i/f, ssram i/f 20pf on sdram i/f 50pf on up i/f notes on d.c. characteristics: 1. input pin or bi-directional pin with internal pull-up resistor. 2. input pin or bi-directional pin without internal pull-up resistor 3. negative currents flow into the device (sinking), positive currents flow out of the device (sourcing).
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 208 20 a.c. timing characteristics (t a = -40c to +85c, v vdd = 3.3 v 0.3v, v pch = 2.5 v 8%) notes on input timing: 1. when a set-up time is specified between an input and a clock, the set-up time is measured from the 50% point of the input to the 50% point of the clock. 2. when a hold time is specified between a clock and an input, the hold time is measured from the 50% point of the clock to the 50% point of the input. notes on output timing: 1. output time is measured between the 50% point of the clock to the 50% point of the output. figure 54 - rstb timing rstb tv rstb table 50 - rtsb timing symbol description min max units tvrstb rstb pulse width 100 ns
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 209 figure 55 - synchronous i/o timing tp tzb tz th ts clk input output table 51 - sysclk timing symbol description min max units f clk frequency, sysclk 40 80 mhz d clk duty cycle,sysclk 40 60 % table 52 - cell buffer sdram interface symbol description min max units ts input set-up time to sysclk 2.4 ns th input hold time to sysclk 0.7 ns tp sysclk high to output valid 1.25 7.0 ns tz sysclk high to output high-impedance 1.25 8.0 ns tzb sysclk high to output driven 1.25 ns maximum output propagation delays are measured with a 20pf load on the outputs. minimum output propagation delays are measured with a 10 pf load on the outputs. table 53 - context memory zbt & late write ssram interface symbol description min max units ts input set-up time to sysclk 2.4 ns
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 210 symbol description min max units th input hold time to sysclk 0.7 ns tp sysclk high to output valid 1.5 8.25 ns tz sysclk high to output high-impedance 1.25 8.25 ns tzb sysclk high to output driven 1.5 ns maximum output propagation delays are measured with a 40pf load on the outputs. minimum output propagation delays are measured with a 0 pf load on the outputs. table 54 - microprocessor interface symbol description min max units f clk frequency, bclk 0 66 mhz d clk duty cycle, bclk 40 60 % ts input set-up time to bclk 3.0 ns th input hold time to bclk 0.1 ns tp bclk high to output valid 2.0 8.0 ns tz bclk high to output high-impedance 2.0 11.0 ns tzb bclk high to output driven 2.0 ns maximum output propagation delays are measured with a 50pf load on the outputs. minimum output propagation delays are measured with a 0 pf load on the outputs. table 55 - loop any-phy transmit interface symbol description min max units f clk ltclk frequency 5 52 d clk ltclk duty cycle 40 60 % ts input set-up time to ltclk 4.0 ns th input hold time to ltclk 0.0 ns
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 211 symbol description min max units tp ltclk high to output valid 1.75 10.0 ns tz ltclk high to output high-impedance 1.75 12.0 ns tzb ltclk high to output driven 1.75 ns maximum output propagation delays are measured with an 80pf load on the loop outputs. minimum output propagation delays are measured with a 0 pf load on the outputs. table 56 - wan any-phy transmit interface symbol description min max units f clk wtclk frequency 0 52 d clk wtclk duty cycle 40 60 % ts input set-up time to wtclk 3.5 ns th input hold time to wtclk 0.0 ns tp wtclk high to output valid 1.75 8.0 ns tz wtclk high to output high-impedance 1.75 12.0 ns tzb wtclk high to output driven 1.75 ns maximum output propagation delays are measured with a 40pf load on the wan outputs. minimum output propagation delays are measured with a 0 pf load on the outputs. table 57 - loop any-phy receive interface symbol description min max units f clk lrclk frequency 0 52 mhz d clk lrclk duty cycle 40 60 % ts input set-up time to lrclk 3.0 ns th input hold time to lrclk 0.25 ns tp lrclk high to output valid 1.75 9.0 ns
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 212 symbol description min max units tz lrclk high to output high-impedance 1.75 12.0 ns tzb lrclk high to output driven 1.75 ns maximum output propagation delays are measured with an 50pf load on the loop outputs. minimum output propagation delays are measured with a 0 pf load on the outputs. table 58 - wan any-phy receive interface symbol description min max units f clk wrclk frequency 0 52 mhz d clk wrclk duty cycle 40 60 % ts input set-up time to wrclk 2.0 ns th input hold time to wrclk 0.35 ns tp wrclk high to output valid 1.75 9.0 ns tz wrclk high to output high-impedance 1.75 12.0 ns tzb wrclk high to output driven 1.75 ns maximum output propagation delays are measured with a 40pf load on the wan outputs. minimum output propagation delays are measured with a 0 pf load on the outputs.
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 213 20.1 jtag interface figure 56 - jtag port interface timing ts tms th tms tms tck ts tdi th tdi tdi tp tdo tdo tck trstb tv trstb table 59 - jtag port interface symbol description min max units tck frequency 5 mhz
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 214 symbol description min max units tck duty cycle 40 60 % tstms tms setup time to tck 50 ns thtms tms hold time to tck 50 ns tstdi tdi setup time to tck 50 ns thtdi tdi hold time to tck 50 ns tptdo tck low to tdo valid 2 50 ns tvtrstb trstb pulse width 100 ns
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 215 21 ordering and thermal information part no. description PM7329-bi 352 ball grid array package (sbga) theta jc < 1 degc/w theta ja degc/w forced air (linear feet per minute) @ 2.86w conv 100 200 300 400 500 dense board 18.5 16.4 15.1 14.2 13.8 13.7 jedec board 13.0 12.0 11.3 10.8 10.3 9.7 notes: 1. dense board is defined as a 3s3p board and consists of a 3x3 array of device PM7329 located as close to each other as board design rules allow. all PM7329 devices are assumed to be dissipating 2.86 watts. ja listed is for the device in the middle of the array. 2. jedec board ja is the measured value for a single thermal device in the same package on a 2s2p board following eia/jesd 51-3
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 216 22 mechanical information figure 57 - mechanical drawing 352 pin ball grid array (sbga)
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 217 notes
PM7329 s/uni-apex-1k800 datasheet pmc-2010141 issue 2 atm traffic manager and switch none of the information contained in this document constitutes an express or implied warranty by pmc-sierra, inc. as to the suf ficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performanc e, compatibility with other parts or systems, of any of the products of pmc-sierra, inc., or any portion thereof, referred to in this document. pmc-sierra, inc. exp ressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. in no event will pmc-sierra, inc. be liable for any direct, indirect, special, incidental or consequential dam ages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not pmc-sierra, inc. has been advi sed of the possibility of such damage. ? 2001 pmc-sierra, inc. pmc-2010141 (r2) issue date: february, 2001 proprietary and confidential to pmc-sierra, inc., and for its customers? internal use contacting pmc-sierra, inc. pmc-sierra, inc. 105-8555 baxter place burnaby, bc canada v5a 4v7 tel: (604) 415-6000 fax: (604) 415-6200 document information: document@pmc-sierra.com corporate information: info@pmc-sierra.com application information: apps@pmc-sierra.com (604) 415-4533 web site: http://www.pmc-sierra.com

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